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Page
Item
396
10.12.3 Pin Functions
522
13.1.2 Block Diagram
523
13.1.3 Pin Configuration
563
15.1 Overview
566
15.1.4 Register Configuration
570, 571
15.2.2 Timer Control/Status Register (TCSR)
573
15.2.4 Pin Function Control Register (PFCR)
587, 588
16.1.4 Register Configuration
597
16.2.6 Serial Control Register (SCR)
646
16.3.5 IrDA Operation
653 to
16.5 Usage Notes
658
18.1.1 Features
692, 693
18.1.2 Block Diagram
694
18.1.3 Input/Output Pins
699, 700
18.2.2 Slave Address Register (SAR)
701
18.2.3 Second Slave Address Register (SARX)
703
18.2.4 I
705, 708,
18.2.5 I
709
2
C Bus Mode Register (ICMR)
2
C Bus Control Register (ICCR)
Revisions
(See Manual for Details)
Table 10-21 Port F Pin Functions
PF3 description amended
Figure 13-1 Block Diagram of 8-Bit
Timer amended
Table 13-1 Pin Configuration
amended
Amended
Table 15-2 WDT Registers
amended
Bits 2 to 0 (overflow period)
amended
Amended
Table 16-2 SCI Registers
Note 3 amended
Description of bits 1 and 0 amended
Figure 16-22 IrDA Transmit and
Receive Operations amended
Operation in Case of Mode
Transition added
Switching from SCK Pin Function to
Port Pin Function added
Formatless description deleted
Description amended
Figure 18-1 Block Diagram of I
Bus Interface
Dedicated formatless clock deleted
2
Table 18-1 I
C Bus Interface Pins
SYNCI pin deleted
Bit 0 description amended
Bit 0 description amended
Description of bits 5 to 3
ø = 25 MHz added to transfer rates
Bit 7 description added
Bit 1 description amended
2
C
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