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7.5.9
Byte Access Control ............................................................................................. 179
7.5.10 Burst Operation..................................................................................................... 181
7.5.11 Refresh Control..................................................................................................... 185
7.6
DMAC Single Address Mode and DRAM Interface ......................................................... 189
7.6.1
DDS=1 .................................................................................................................. 189
7.6.2
DDS=0 .................................................................................................................. 190
7.7
Burst ROM Interface.......................................................................................................... 191
7.7.1
Overview............................................................................................................... 191
7.7.2
Basic Timing......................................................................................................... 191
7.7.3
Wait Control.......................................................................................................... 193
7.8
Idle Cycle ........................................................................................................................... 194
7.8.1
Operation .............................................................................................................. 194
7.8.2
Pin States in Idle Cycle ......................................................................................... 198
7.9
Write Data Buffer Function ............................................................................................... 199
7.10 Bus Release........................................................................................................................ 200
7.10.1 Overview............................................................................................................... 200
7.10.2 Operation .............................................................................................................. 200
7.10.3 Pin States in External Bus Released State ............................................................ 201
7.10.4 Transition Timing ................................................................................................. 202
7.10.5 Notes ..................................................................................................................... 203
7.11 Bus Arbitration................................................................................................................... 204
7.11.1 Overview............................................................................................................... 204
7.11.2 Operation .............................................................................................................. 204
7.11.3 Bus Transfer Timing ............................................................................................. 205
7.12 Resets and the Bus Controller............................................................................................ 205
Section 8
DMA Controller
8.1
Overview............................................................................................................................ 207
8.1.1
Features ................................................................................................................. 207
8.1.2
Block Diagram...................................................................................................... 208
8.1.3
Overview of Functions.......................................................................................... 209
8.1.4
Pin Configuration.................................................................................................. 211
8.1.5
Register Configuration.......................................................................................... 212
8.2
Register Descriptions (1) (Short Address Mode)............................................................... 213
8.2.1
Memory Address Registers (MAR)...................................................................... 214
8.2.2
I/O Address Register (IOAR) ............................................................................... 215
8.2.3
Execute Transfer Count Register (ETCR)............................................................ 215
8.2.4
DMA Control Register (DMACR) ....................................................................... 216
8.2.5
DMA Band Control Register (DMABCR) ........................................................... 220
8.3
Register Descriptions (2) (Full Address Mode) ................................................................. 225
8.3.1
Memory Address Register (MAR)........................................................................ 225
8.3.2
I/O Address Register (IOAR) ............................................................................... 225
8.3.3
Execute Transfer Count Register (ETCR)............................................................ 226
.............................................................................................. 207
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