Advertisement
18.2 Register Descriptions ......................................................................................................... 696
2
18.2.1 I
C Bus Data Register (ICDR).............................................................................. 696
18.2.2 Slave Address Register (SAR).............................................................................. 699
18.2.3 Second Slave Address Register (SARX).............................................................. 700
2
18.2.4 I
C Bus Mode Register (ICMR)............................................................................ 701
2
18.2.5 I
C Bus Control Register (ICCR).......................................................................... 704
2
18.2.6 I
C Bus Status Register (ICSR) ............................................................................ 711
18.2.7 Serial Control Register X (SCRX)........................................................................ 716
18.2.8 DDC Switch Register (DDCSWR)....................................................................... 717
18.2.9 Module Stop Control Register B (MSTPCRB) .................................................... 718
18.3 Operation............................................................................................................................ 719
2
18.3.1 I
C Bus Data Format ............................................................................................. 719
18.3.2 Master Transmit Operation ................................................................................... 720
18.3.3 Master Receive Operation .................................................................................... 722
18.3.4 Slave Receive Operation....................................................................................... 724
18.3.5 Slave Transmit Operation ..................................................................................... 726
18.3.6 IRIC Setting Timing and SCL Control ................................................................. 728
18.3.7 Operation Using the DTC ..................................................................................... 729
18.3.8 Noise Canceler...................................................................................................... 730
18.3.9 Sample Flowcharts................................................................................................ 730
18.3.10 Initialization of Internal State ............................................................................... 734
18.4 Usage Notes ....................................................................................................................... 736
Section 19 A/D Converter
19.1 Overview............................................................................................................................ 745
19.1.1 Features ................................................................................................................. 745
19.1.2 Block Diagram...................................................................................................... 746
19.1.3 Pin Configuration.................................................................................................. 747
19.1.4 Register Configuration.......................................................................................... 748
19.2 Register Descriptions ......................................................................................................... 749
19.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 749
19.2.2 A/D Control/Status Register (ADCSR) ................................................................ 750
19.2.3 A/D Control Register (ADCR) ............................................................................. 753
19.2.4 Module Stop Control Register A (MSTPCRA).................................................... 754
19.3 Interface to Bus Master...................................................................................................... 755
19.4 Operation............................................................................................................................ 756
19.4.1 Single Mode (SCAN = 0) ..................................................................................... 756
19.4.2 Scan Mode (SCAN = 1)........................................................................................ 758
19.4.3 Input Sampling and A/D Conversion Time .......................................................... 760
19.4.4 External Trigger Input Timing.............................................................................. 761
19.5 Interrupts ............................................................................................................................ 762
19.6 Usage Notes ....................................................................................................................... 762
.................................................................................................. 745
xiii
Advertisement
