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11.2.8 Timer Start Register (TSTR) ................................................................................ 441
11.2.9 Timer Synchro Register (TSYR) .......................................................................... 442
11.2.10 Module Stop Control Register A (MSTPCRA).................................................... 443
11.3 Interface to Bus Master...................................................................................................... 444
11.3.1 16-Bit Registers .................................................................................................... 444
11.3.2 8-Bit Registers ...................................................................................................... 444
11.4 Operation............................................................................................................................ 446
11.4.1 Overview............................................................................................................... 446
11.4.2 Basic Functions..................................................................................................... 447
11.4.3 Synchronous Operation ........................................................................................ 453
11.4.4 Buffer Operation ................................................................................................... 455
11.4.5 Cascaded Operation .............................................................................................. 459
11.4.6 PWM Modes ......................................................................................................... 461
11.4.7 Phase Counting Mode ........................................................................................... 466
11.5 Interrupts ............................................................................................................................ 473
11.5.1 Interrupt Sources and Priorities ............................................................................ 473
11.5.2 DTC/DMAC Activation........................................................................................ 475
11.5.3 A/D Converter Activation..................................................................................... 475
11.6 Operation Timing ............................................................................................................... 476
11.6.1 Input/Output Timing ............................................................................................. 476
11.6.2 Interrupt Signal Timing ........................................................................................ 480
11.7 Usage Notes ....................................................................................................................... 484
Section 12 Programmable Pulse Generator (PPG)
12.1 Overview............................................................................................................................ 495
12.1.1 Features ................................................................................................................. 495
12.1.2 Block Diagram...................................................................................................... 496
12.1.3 Pin Configuration.................................................................................................. 497
12.1.4 Registers................................................................................................................ 498
12.2 Register Descriptions ......................................................................................................... 499
12.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 499
12.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 500
12.2.3 Next Data Registers H and L (NDRH, NDRL) .................................................... 501
12.2.4 Notes on NDR Access .......................................................................................... 501
12.2.5 PPG Output Control Register (PCR) .................................................................... 503
12.2.6 PPG Output Mode Register (PMR) ...................................................................... 505
12.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 508
12.2.8 Module Stop Control Register A (MSTPCRA).................................................... 508
12.3 Operation............................................................................................................................ 509
12.3.1 Overview............................................................................................................... 509
12.3.2 Output Timing ...................................................................................................... 510
12.3.3 Normal Pulse Output ............................................................................................ 511
12.3.4 Non-Overlapping Pulse Output ............................................................................ 513
..................................................... 495
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