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Type
Symbol
Interrupts
NMI
IRQ7 to IRQ0 Input
Address bus
A23 to A0
Data bus
D15 to D0
CS7 to CS0
Bus control
AS
RD
HWR
LWR
CAS
LCAS
OE
WAIT
16
I/O
Name and Function
Input
Nonmaskable interrupt: Requests a nonmaskable
interrupt. When this pin is not used, it should be fixed
high.
Interrupt request 7 to 0: These pins request a
maskable interrupt.
Output
Address bus: These pins output an address.
I/O
Data bus: These pins constitute a bidirectional data
bus.
Output
Chip select: Selection signal for areas 0 to 7.
Output
Address strobe: When this pin is low, it indicates that
address output on the address bus is enabled.
Output
Read: When this pin is low, it indicates that the
external address space can be read.
Output
High write/write enable/upper write enable:
A strobe signal that writes to external space and
indicates that the upper half (D15 to D8) of the data
bus is enabled.
The 2CAS type DRAM write enable signal.
The 2WE type DRAM upper write enable signal.
Output
Low write/lower column address strobe/lower write
enable:
A strobe signal that writes to external space and
indicates that the lower half (D7 to D0) of the data bus
is enabled.
The 2CAS type (LCASS = 1) DRAM lower column
address strobe signal.
The 2WE type DRAM lower write enable signal.
Output
Upper column address strobe/column address strobe:
The 2CAS type DRAM upper column address strobe
signal.
Output
Lower column address strobe:
The 2CAS type DRAM lower column address strobe
signal.
Output
Output enable:
Output enable signal for DRAM space read access.
Input
Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address space.
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