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8.3.4
DMA Control Register (DMACR) ....................................................................... 227
8.3.5
DMA Band Control Register (DMABCR) ........................................................... 231
8.4
Register Descriptions (3) ................................................................................................... 236
8.4.1
DMA Write Enable Register (DMAWER)........................................................... 236
8.4.2
DMA Terminal Control Register (DMATCR) ..................................................... 238
8.4.3
Module Stop Control Register (MSTPCR)........................................................... 239
8.5
Operation............................................................................................................................ 240
8.5.1
Transfer Modes ..................................................................................................... 240
8.5.2
Sequential Mode ................................................................................................... 242
8.5.3
Idle Mode.............................................................................................................. 245
8.5.4
Repeat Mode ......................................................................................................... 248
8.5.5
Single Address Mode............................................................................................ 252
8.5.6
Normal Mode........................................................................................................ 255
8.5.7
Block Transfer Mode............................................................................................ 258
8.5.8
DMAC Activation Sources ................................................................................... 264
8.5.9
Basic DMAC Bus Cycles...................................................................................... 267
8.5.10 DMAC Bus Cycles (Dual Address Mode)............................................................ 268
8.5.11 DMAC Bus Cycles (Single Address Mode) ......................................................... 276
8.5.12 Write Data Buffer Function .................................................................................. 282
8.5.13 DMAC Multi-Channel Operation ......................................................................... 283
8.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,
and the DMAC...................................................................................................... 285
8.5.15 NMI Interrupts and DMAC .................................................................................. 286
8.5.16 Forced Termination of DMAC Operation ............................................................ 287
8.5.17 Clearing Full Address Mode................................................................................. 288
8.6
Interrupts ............................................................................................................................ 289
8.7
Usage Notes ....................................................................................................................... 290
Section 9
Data Transfer Controller (DTC)
9.1
Overview............................................................................................................................ 295
9.1.1
Features ................................................................................................................. 295
9.1.2
Block Diagram...................................................................................................... 296
9.1.3
Register Configuration.......................................................................................... 297
9.2
Register Descriptions ......................................................................................................... 298
9.2.1
DTC Mode Register A (MRA) ............................................................................. 298
9.2.2
DTC Mode Register B (MRB).............................................................................. 300
9.2.3
DTC Source Address Register (SAR) .................................................................. 301
9.2.4
DTC Destination Address Register (DAR) .......................................................... 301
9.2.5
DTC Transfer Count Register A (CRA) ............................................................... 301
9.2.6
DTC Transfer Count Register B (CRB)................................................................ 302
9.2.7
DTC Enable Registers (DTCER).......................................................................... 302
9.2.8
DTC Vector Register (DTVECR) ........................................................................ 303
9.2.9
Module Stop Control Register A (MSTPCRA).................................................... 304
vi
................................................................. 295
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