Timer Setting Register (Txtcr) - Fujitsu MB91319 Series Hardware Manual

CHAPTER 7 MULTIFUNCTION TIMER
7.2.3

Timer Setting Register (TxTCR)

The timer setting register (TxTCR) controls the timer operation.
■ Timer Setting Register (TxTCR)
The timer setting register (TxTCR) can be 8-bit accessed. If this register is rewritten during
operation (entire register ST = 1), the timer operation is unpredictable. Be sure to rewrite this
register when it is stopped (ST = 0).
Figure 7.2-4 shows the bit configuration of the timer setting register (TxTCR).
Figure 7.2-4 Bit Configuration of the Timer Setting Register (TxTCR)
TxTCR 0000F2
address 0000FA
000102
00010A
[bit15] TCF (timer compare match detection flag)
This bit indicates that a timer compare match has been detected.
0
1
Writing 1 to this bit has no effect.
If data is written to this bit from the hardware and the CPU at the same time, writing data from
the hardware has priority.
[bit14] TSES (timer start edge select flag)
This bit sets the start edge of the timer.
0
1
[bit13] TCC (timer count clear setting flag)
This bit specifies that the counter is cleared when a timer compare match is detected.
0
1
176
15 14 13
H
H
TCF TSES TCC
H
H
R/W R/W R/W
No compare match [initial value]
Compare match
Rising edge [initial value]
Falling edge
Count clear [initial value]
No count clear
12 11 10 9
TIE CINV TCS2 TCS1 TCS0
R/W R/W R/W R/W
Initial value
8
00000000
B
R/W