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[bit8] TFE (Transmission FIFO empty flag)
This indicates the FIFO is empty at the time of transmission.
0
1
The data is not in FIFO at data transmission, and if 1-byte transfer including acknowledge bit
is ended, the interrupt source bit is set.
When the data is in FIFO, writing '0' to the INT bit is cleared. Writing the MSS or SCC bit to 0
and 1, respectively is cleared.
■
IFRN (FIFO Reception Count Register)
Address:
ch0 0000B1
ch1 0000C1
ch2 0000D1
ch3 0000E1
Write to this register when the FEN and INT is set to 1.
[bit7] FACK (FIFO reception acknowledge)
0
1
This flag is allowed when ACK is set to 1. Acknowledge is occurred when the data other than
FRN=1 is received.
When the data of FRN=1 is received, acknowledge is output according to this bit. Writing is
performed when INT=1.
[bit3 to bit0] FRN3 to FRN0 (Reception data count bit)
This register sets the number of received data. The register is decremented to FIFO every 1-
byte reception. Writing 0000
data is read. When the FRN is changed from 1 to 0, the INT becomes 1. When INT=1, write
operation is performed.
Data exists in FIFO at transmission.
Data does not exist in FIFO at transmission.
Figure 15.2-17 IFRN (FIFO Reception Count Register)
7
H
FACK
H
H
R/W
Initial value
H
0
Acknowledge is not generated when data of FRN=1 is received.
Acknowledge is generated when data of FRN=1 is received.
is 16-byte reception. At reading, number of remaining reception
B
6
5
4
3
FRN3 FRN2 FRN1 FRN0
R/W
R/W
R/W
R/W
0
0
0
0
2
CHAPTER 15 I
C INTERFACE
2
1
0
R/W
R/W
R/W
0
0
0
309
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