Fujitsu MB91319 Series Hardware Manual page 461

Fr60 32-bit microcontroller
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Figure 17.4-2 Timing Diagram for BULK OUT Transfer (Reading by CPU and Writing by USB)
PACKET N
Writing by
FIFO (a)
USB
1)
FIFO (b)
IRQ
CPU bus side
1)
2)
PACKET N
3)
4)
5)
PACKET N+1
Shading indicates
existence of data.
PACKET N+1
Reading by
CPU
3)
ACK1
Writing by
USB
2)
NACK1
FIFO (a)
Reading disabled
FIFO (b)
Reading enabled
FIFO (a)
FIFO (b)
FIFO (a)
Reading disabled
FIFO (b)
FIFO (a)
Reading disabled
FIFO (b)
FIFO (a)
FIFO (b)
Reading enabled
CHAPTER 17 USB FUNCTION
PACKET N+1
PACKET N+2
Writing by
USB
4)
5)
Writing by
Reading by
USB
CPU
ACK2
USB bus side
PACKET N
PACKET N+1
PACKET N+1
PACKET N+1
PACKET N+2
Reading by
CPU
ACK1
NACK
ACK2
439

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