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CHAPTER 14 UART
■ Functions of Bits in the Serial Status Register (SSR)
The following describes the functions of the serial status register (SSR) bits.
[bit7] PE (Parity Error)
This bit, which is an interrupt request flag, is set when a parity error occurs during reception.
To clear the flag when it has been set, write 0 to the REC bit (bit10) of the SCR register.
If the PE bit is set, the SIDR data becomes invalid.
Table 14.2-10 shows the parity error interrupt request flag.
Table 14.2-10 Parity Error Interrupt Request Flag
PE
0
1
[bit6] ORE (Over Run Error)
This bit, which is an interrupt request flag, is set when an overrun error occurs during
reception.
To clear the flag when it has been set, write 0 to the REC bit of the SCR register.
If the ORE bit is set, the SIDR data becomes invalid.
Table 14.2-11 shows the overrun error interrupt request flag.
Table 14.2-11 Overrun Error Interrupt Request Flag
ORE
0
1
[bit5] FRE (FRaming Error)
This bit, which is an interrupt request flag, is set when a framing error occurs during reception.
To clear the flag when it has been set, write 0 to the REC bit of the SCR register.
If the FRE bit is set, the SIDR data becomes invalid.
Table 14.2-12 shows the framing error interrupt request flag.
Table 14.2-12 Framing Error Interrupt Request Flag
FRE
0
1
Note:
Switch the internal and external baud rate clocks using bit3 of the serial mode register only while the
UART is stopped, since the switching takes effect immediately after writing.
Bit3 of the serial mode register is write-only.
266
Occurrence of parity error
No parity error has occurred.
A parity error has occurred.
Occurrence of overrun error
No overrun error has occurred.
An overrun error has occurred.
Occurrence of framing error
No framing error has occurred.
A framing error has occurred.
[initial value]
[initial value]
[initial value]
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