Fujitsu MB91319 Series Hardware Manual page 310

2
CHAPTER 15 I C INTERFACE
(Continued)
7-bit slave address register (ISBA)
Address:
ch0 0000BB
ch1 0000CB
ch2 0000DB
ch3 0000EB
7-bit slave address mask register (ISMK)
Address:
ch0 0000BA
ch1 0000CA
ch2 0000DA
ch3 0000EA
Data register (IDAR)
Address:
ch0 0000BD
ch1 0000CD
ch2 0000DD
ch3 0000ED
Clock control register (ICCR)
Address:
ch0 0000BE
ch1 0000CE
ch2 0000DE
ch3 0000EE
FIFO data count register (IFN)
Address:
ch0 0000B0
ch1 0000C0
ch2 0000D0
ch3 0000E0
FIFO reception register (IFRN)
Address:
ch0 0000B1
ch1 0000C1
ch2 0000D1
ch3 0000E1
FIFO control register (IFCR)
Address:
ch0 0000B2
ch1 0000C2
ch2 0000D2
ch3 0000E2
FIFO data register (IFDR)
Address:
ch0 0000B3
ch1 0000C3
ch2 0000D3
ch3 0000E3
288
7
H
H
H R
H Initial value 0
15
H
ENSB SM6
H
R/W
H
Initial value 0
H
7
H
D7
H
R/W
H
Initial value
H 0
15
H
TEST
H
H W
H Initial value
0
15
H
H
R
H
Initial value 0
H
7
H
FACK FRN6 FRN5
H
R/W
H
0
H Initial value
15
H
FEN
H
R/W
H
Initial value 0
H
7
H
FD7
H
R/W R/W
H
Initial value 0
H
6 5 4
SA6 SA5 SA4
R/W R/W R/W
0 0 0
14 13 12 11
SM5 SM4 SM3
R/W R/W R/W R/W
1 1 1 1
6 5 4
D6 D5 D4
R/W R/W R/W R/W
0 0 0
14 13 12 11
NSF EN CS4 CS3
R/W R/W R/W R/W
0 0 1
14 13 12 11
FN4 FN3
R R R R
0 0 0 0
6 5 4
FRN4 FRN3 FRN2
R/W R/W R/W R/W
0 0 0
14 13 12 11
FCL TEDIE FER
R/W - R/W R/W
0 - 0 0
6 5 4 3
FD6 FD5 FD4 FD3
R/W R/W R/W
0 0 0 0
3 2 1 0
SA3 SA2 SA1 SA0
R/W R/W R/W R/W
0 0 0 0
10 9 8
SM2 SM1 SM0
R/W R/W R/W
1 1 1
3 2 1 0
D3 D2 D1 D0
R/W R/W R/W
0 0 0 0
10 9 8
CS2 CS1 CS0
R/W R/W R/W
1 1 1 1
10 9 8
FN2 FN1 FN0
R R R
0 0 0
3 2 1 0
FRN1 FRN0
R/W R/W R/W
0 0 0 0
10 9 8
TED FRED TFE
R R R
0 0 0
2 1 0
FD2 FD1 FD0
R/W R/W R/W
0 0 0