Fujitsu MB91319 Series Hardware Manual page 587

Line width
No line spacing
Upper line spacing
Line width
Line spacing specified
Lower line spacing
Line width
No line spacing
❍ Vertical synchronization signal input flag
The trailing edge of the internal vertical synchronization signal is detected.
The point where a vertical synchronization signal as shown in Figure 18.3-16 is detected
becomes a factor of vertical synchronization signal input.
Figure 18.3-16 Vertical Synchronization Signal Detection
VSYNC input
(VSYNC pin)
OSDC
Internal VSYNC
Point of vertical
synchronization
signal detection
❍ VRAM fill end flag
The end of VRAM setting started by a VRAM fill command (command 0 to 2) becomes a factor of
VRAM fill end.
Figure 18.3-15 Line Display End Detection
Line end detection line
Line address: AY=0×0 (top line)
Line end detection line
Line address: AY=0×1
Line end detection line
∗
Line address: AY=0×2 to 0×E is omitted.
Line end detection line
Line address: AY=0×F (last line)
Line end detection line
CHAPTER 18 OSDC
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