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❍ For fly-by transfer
For a demand transfer, be sure to set an address in an external area for the transfer destination.
•
For fly-by (timing to read pin) transfer:
After the IOWR pin output for the last DMA transfer goes to the H level, negate DREQ while
the external RD pin output is at the L level.
If DREQ is negated after the period when DACK and RD are at the L level, the next transfer
may be executed.
•
For fly-by (timing to IORD pin) transfer:
After the external WR pin output for the last DMA transfer goes to the H level, negate DREQ
while IORD is at the L level.
If DREQ is negated after the period when DACK and IORD are at the L level, the next transfer
may be executed.
Figure 16.3-7 shows an example of the timing for negating the DREQ pin input for fly-by (write)
transfer.
Figure 16.3-7 Example of the Timing for Negating the DREQ Pin Input for Fly-by (Timing to IORD Pin)
Transfer
External bus clock
CS0
CS1
AS
RD
WRn
DREQn
DACKn
IORD
Negate the range of DERQ pin input indicated with the arrow. If you set the negation timing later
than the circular mark
, an extra round of signal may be transferred.
CHAPTER 16 DMA CONTROLLER (DMAC)
367
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