Fujitsu MB90390 Series Hardware Manual

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FUJITSU MICROELECTRONICS

CM44-10122-4E

CONTROLLER MANUAL

MC-16LX

16-BIT MICROCONTROLLER

MB90390 Series

HARDWARE MANUAL

Table of Contents

Summary of Contents for Fujitsu MB90390 Series

Page 1 FUJITSU MICROELECTRONICS CM44-10122-4E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90390 Series HARDWARE MANUAL...
Page 3 MC-16LX 16-BIT MICROCONTROLLER MB90390 Series HARDWARE MANUAL The information for microcontroller supports is shown in the following homepage. Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet"...
Page 5 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC). This manual explains the functions and operation of the MB90390 series for designers who actually use the MB90390 series to design products. Please read this manual first.
Page 6 CHAPTER 8 LOW-POWER CONTROL CIRCUIT This chapter explains the functions and operations of the low-power control circuits. CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. CHAPTER 11 TIME-BASE TIMER This chapter explains the functions and operations of the time-base timer.
Page 7 CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and operation. CHAPTER 27 ROM MIRRORING MODULE This chapter explains the ROM mirroring module. CHAPTER 28 3M-BIT FLASH MEMORY This chapter explains the functions and operation of the 3M-bit flash memory. CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION This chapter provides examples of F2MC-16LX MB90F394H(A) serial programming connection.
Page 8 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third- party's intellectual property right or other right by using such information.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ....................1 Product Overview ..........................2 Features .............................. 3 Block Diagram of MB90V390H ......................6 Block Diagram of MB90V390HA/MB90V390HB ................. 7 Block Diagram of MB90394HA/MB90F394H(A) ................. 8 Pin Assignment ........................... 9 Package Dimensions ........................12 Pin Functions ............................ 13 Input-Output Circuits .........................
Page 10 Exceptions ............................80 CHAPTER 4 DELAYED INTERRUPT ................81 Outline of Delayed Interrupt Module ....................82 Delayed Interrupt Register ........................ 83 Delayed Interrupt Operation ......................84 CHAPTER 5 CLOCKS ..................... 85 Clocks ............................... 86 Block Diagram of the Clock Generation Block .................. 89 Clock Selection Registers .........................
Page 11 CHAPTER 9 MEMORY ACCESS MODES ..............163 Outline of Memory Access Modes ....................164 Mode Pins of Memory Access Mode ....................165 Mode Data of Memory Access Mode ....................166 CHAPTER 10 I/O PORTS ....................169 10.1 I/O Ports ............................170 10.2 I/O Port Registers ...........................
Page 12 CHAPTER 15 WATCH TIMER ..................237 15.1 Outline of Watch Timer ........................238 15.2 Watch Timer Registers ........................239 15.2.1 Timer Control Register ......................240 15.2.2 Sub-second Registers ....................... 244 15.2.3 Second/Minute/Hour Registers ....................245 CHAPTER 16 8/16-BIT PPG ................... 247 16.1 Outline of 8/16-bit PPG ........................
Page 13 CHAPTER 19 UART0, UART1 ..................311 19.1 Features of UART0, UART1 ......................312 19.2 UART0, UART1 Block Diagram ...................... 313 19.3 UART0, UART1 Registers ......................314 19.3.1 Serial Mode Control Register (UMC) ..................315 19.3.2 Status Register (USR) ....................... 317 19.3.3 Input Data Register (UIDR) and Output Data Register (UODR) ..........
Page 14 20.8 Notes on Using UART2, UART3 ..................... 401 CHAPTER 21 400 kHz I C INTERFACE ................. 405 21.1 C Interface Overview ........................406 21.2 C Interface Registers ........................408 21.2.1 Bus Status Register (IBSR) ....................... 410 21.2.2 Bus Control Register (IBCR) ..................... 413 21.2.3 Ten Bit Slave Address Register (ITBA) ..................
Page 15 23.6.13 Transmission Interrupt Enable Register (TIER) ................. 486 23.6.14 Reception Complete Register (RCR) ..................487 23.6.15 Remote Request Receiving Register (RRTRR) ................ 488 23.6.16 Receive Overrun Register (ROVRR) ..................489 23.6.17 Reception Interrupt Enable Register (RIER) ................490 23.6.18 Acceptance Mask Select Register (AMSR) ................491 23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) ............
Page 16 27.2 ROM Mirroring Register (ROMM) ....................553 CHAPTER 28 3M-BIT FLASH MEMORY ................ 555 28.1 Overview of 3M-bit Flash Memory ....................556 28.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory ..557 28.3 Write/Erase Modes .........................
Page 17 APPENDIX D List of Interrupt Vectors ......................690 INDEX........................... 695 xiii...
Page 19 (UART3 synchronous clock mode → UART2, UART3 synchronous clock mode) (3M/4M-BIT FLASH MEMORY → 3M-BIT FLASH MEMORY) Table 1.2-1 Features of the MB90390 Series (1/3) is changed. (UART of MB90V390H : 3 channels → 2 channels) Table 1.2-1 Features of the MB90390 Series (2/3) is changed.
Page 20 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) ● Crystal Oscillator Circuit is changed. (Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is added.) ● Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs is changed. ((turning on/off the analog and digital power supplies simultaneously is acceptable) is deleted.) ●...
Page 21 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) Table 13.5-3 Input Capture Edge Register Bits (Upper and Lower) Bit name of bit10 is changed. (IUCE → IUCE1/IUCE5) bit2 is changed. Figure 14.5-1 Output Pin Function of 16-bit Reload Timer (1) is changed. Figure 14.5-2 Output Pin Function of 16-bit Reload Timer (2) is changed.
Page 22 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) Table 16.3-3 Bit Function Description of the Clock Select Register (PPG01) PCS1 and PCM1 in "Clock input from time-base timer" are changed. (0 → 1) ■ Reload Register (PRLL/PRLH) Address of PRLLn is changed.
Page 23 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) Figure 19.3-1 Configuration of the Serial Mode Control Register (UMC) is changed. (UMC2 is deleted.) (000028 is deleted.) Serial Output enable is changed. (SOT0,1,2 → SOT0, SOT1) Table 19.3-1 Function of Each Bit of the Serial Control Register Function of bit1 and bit0 is changed.
Page 24 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) Figure 20.4-5 Transmission and Reception Data Registers (RDR2/RDR3 and TDR2/TDR3) is changed. (RDR2/TDR2: 0035DA is changed.) ("0 0 0 0 0 0 0 0 [TDR3] (MB90V390H/MB90F394H)" is deleted.) Summary of 20.4.5 Extended Status/Control Register (ESCR2/ESCR3) is changed.
Page 25 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) ● Reception operation is changed. (To read received data, check the error flag status upon completion of reception of one-frame data and, if the data has been received normally, read the received data from the Reception Data Register (RDR2/RDR3). If a reception error has occurred, perform error handling.
Page 26 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) Figure 20.7-16 Settings for UART2, UART3 in Operation Mode 3 (LIN) Mode3 of EXT is changed. → 0) Mode3 of SCKE is changed. → 0) Mode3 of SCES is changed. (0 →...
Page 27 ("Sector Erase Suspend command should be entered more than 20µs after Sector Erase command or Sector Erase Restart command is issued." is added) ● Input of a hardware reset (RST) is changed. Table 29.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming Additional information of VCC is changed. Table A-1 I/O Map (1/6) Register of Address 00000D is changed.
Page 28 Reference: Main changes (Rev.2 → Rev.3) Page Changes (For details, refer to main body.) Table A-2 I/O Map (35XX Addresses) (2/8) Initial value of Address 00351A is changed. (11111111 is added.) Initial value of Address 00351C is changed. → X0000XXX (000000XX Abbreviation of Address 00352E is changed.
Page 29: Chapter 1 Overview
CHAPTER 1 OVERVIEW The MB90390 Series is a family member of the F 16LX microcontrollers. 1.1 Product Overview 1.2 Features 1.3 Block Diagram of MB90V390H 1.4 Block Diagram of MB90V390HA/MB90V390HB 1.5 Block Diagram of MB90394HA/MB90F394H(A) 1.6 Pin Assignment 1.7 Package Dimensions 1.8 Pin Functions...
Page 30: Product Overview
CHAPTER 1 OVERVIEW Product Overview Table 1.1-1 lists the product overview. ■ Product Overview Table 1.1-1 Product Overview MB90V390H Features MB90V390HA MB90394HA MB90F394H(A) MB90V390HB Product type Evaluation sample ROM version Flash version MC-16LX CPU On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stop) System clock Minimum instruction execution time: 42 ns (4 MHz osc.
Page 31: Features
CHAPTER 1 OVERVIEW Features Table 1.2-1 lists the features of the MB90390 series. ■ Features Table 1.2-1 Features of the MB90390 Series (1/3) MB90V390H Features MB90V390HA MB90394HA MB90F394H(A) MB90V390HB 2 channels Full duplex double buffer UART Supports asynchronous/synchronous (with start/stop bit) transfer...
Page 32 CHAPTER 1 OVERVIEW Table 1.2-1 Features of the MB90390 Series (2/3) MB90V390H Features MB90V390HA MB90394HA MB90F394H(A) MB90V390HB Rising edge, falling edge or rising & falling edge sensitive 16-bit Input Six 16-bit Capture registers Capture Signals an interrupt upon external event...
Page 33 CHAPTER 1 OVERVIEW Table 1.2-1 Features of the MB90390 Series (3/3) MB90V390H Features MB90V390HA MB90394HA MB90F394H(A) MB90V390HB Supports automatic programming, Embedded Algorithm Write/Erase/ Erase-Suspend/Resume commands. A flag indicating completion of the algorithm Number of erase cycles: 10,000 times. Data retention time: 20 years *...
Page 34: Block Diagram Of Mb90V390H
CHAPTER 1 OVERVIEW Block Diagram of MB90V390H Figure 1.3-1 shows a block diagram of the MB90V390H. ■ Block Diagram of MB90V390H Figure 1.3-1 Block Diagram of MB90V390H X0,X1 Clock 16LX Controller IO Timer0 FRCK0 Input Capture IN[5:0] 16KBytes Output Compare OUT[7:0] Prescaler x4* IO Timer1...
Page 35: Block Diagram Of Mb90V390Ha/Mb90V390Hb
CHAPTER 1 OVERVIEW Block Diagram of MB90V390HA/MB90V390HB Figure 1.4-1 shows a block diagram of the MB90V390HA/MB90V390HB devices. ■ Block Diagram of MB90V390HA/MB90V390HB Figure 1.4-1 Block Diagram of MB90V390HA/MB90V390HB X0,X1 Clock 16LX Controller IO Timer0 FRCK0 Input Capture IN[5:0] 30KBytes Output Compare OUT[7:0] Prescaler x4*...
Page 36: Block Diagram Of Mb90394Ha/Mb90F394H(A)
CHAPTER 1 OVERVIEW Block Diagram of MB90394HA/MB90F394H(A) Figure 1.5-1 shows a block diagram of the MB90394HA/MB90F394H(A) devices. ■ Block Diagram of MB90394HA/MB90F394H(A) Figure 1.5-1 Block Diagram of MB90394HA/MB90F394H(A) X0,X1 Clock 16LX Controller IO Timer0 FRCK0 Input 10KBytes Capture IN[5:0] ROM/Flash Output 384KBytes Compare...
Page 37: Pin Assignment
P50/PPG10 P84/PWM1P3 As seen with LQFP-120 probe cable P51/PPG11 P83/PWM2M2 P52/PPG12 P82/PWM2P2 P53/PPG13 P81/PWM1M2 P54/PPG14 P80/PWM1P2 P55/PPG15 P56/PPG00/RX2 P57/PPG01/TX2 P77/PWM2M1 P90/SIN2 P76/PWM2P1 P91/SCK2 P75/PWM1M1 P92/SOT2 P74/PWM1P1 Note: In other devices of the MB90390 series some pin functions are not available.
Page 38 CHAPTER 1 OVERVIEW ■ Pin Assignment of MB90V390HA/MB90V390HB Figure 1.6-2 Pin Assignment of MB90V390HA/MB90V390HB P30/RX0 P31/TX0 P32/TIN1 P33/TOT1 P34/SOT0 P35/SCK0 P36/SIN0 PA7/PWM2M5 P37/SIN1 PA6/PWM2P5 P40/SCK1 PA5/PWM1M5 P41/SOT1 PA4/PWM1P5 P42/SDA PA3/PWM2M4 MB90V390HA/HB P43/SCL PA2/PWM2P4 Pin Assignment PA1/PWM1M4 P45/ADTG PA0/PWM1P4 P87/PWM2M3 P46/INT0 P86/PWM2P3 P47/INT1 P85/PWM1M3...
Page 39 CHAPTER 1 OVERVIEW ■ Pin Assignment of MB90394HA/MB90F394H(A) Figure 1.6-3 Pin Assignment of MB90394HA/MB90F394H(A) P30/RX0 P31/TX0 P32/TIN1 P33/TOT1 P34/SOT0 P35/SCK0 P36/SIN0 PA7/PWM2M5 P37/SIN1 PA6/PWM2P5 P40/SCK1 PA5/PWM1M5 P41/SOT1 PA4/PWM1P5 P42/SDA* PA3/PWM2M4 MB90394HA/MB90F394H(A) P43/SCL* PA2/PWM2P4 Pin Assignment PA1/PWM1M4 P45/ADTG PA0/PWM1P4 P87/PWM2M3 P46/INT0 P86/PWM2P3 P47/INT1 P85/PWM1M3...
Page 40: Package Dimensions
(Stand off) 0.60±0.15 0.22±0.05 0.145 –0.03 0.50(.020) 0.08(.003) (.024±.006) (.009±.002) +.002 .006 –.001 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are ref erence values. 2002 FUJITSU LIMITED F120033S-c-4-4 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...
Page 41: Pin Functions
CHAPTER 1 OVERVIEW Pin Functions Table 1.8-1 lists the pin description. ■ Pin Functions Table 1.8-1 Pin Description (1/6) Pin No. Pin name Circuit type Function Oscillation output Oscillation input Reset input P00 to P02 General purpose I/O 93 to 95 IN0 to IN2 Inputs for the Input Captures 0 to 2 General purpose I/O...
Page 42 CHAPTER 1 OVERVIEW Table 1.8-1 Pin Description (2/6) Pin No. Pin name Circuit type Function General purpose I/O TX output for CAN Interface 1 General purpose I/O RX input for CAN Interface 1 P22 to P27 General purpose I/O 115 to 120 INT2 to INT7 External interrupt inputs for INT2 to INT7 General purpose I/O...
Page 43 CHAPTER 1 OVERVIEW Table 1.8-1 Pin Description (3/6) Pin No. Pin name Circuit type Function General purpose I/O ADTG External trigger input of the A/D Converter P46, P47 General purpose I/O 18, 19 INT0, INT1 External interrupt inputs for INT0, INT1 P50 to P55 General purpose I/O 20 to 25...
Page 44 CHAPTER 1 OVERVIEW Table 1.8-1 Pin Description (4/6) Pin No. Pin name Circuit type Function General purpose I/O PPG02 Output for the Programmable Pulse Generator 2 TX output for CAN Interface 3 Input for the A/D Converter General purpose I/O PPG03 Output for the Programmable Pulse Generator 3 RX input for CAN Interface 3...
Page 45 CHAPTER 1 OVERVIEW Table 1.8-1 Pin Description (5/6) Pin No. Pin name Circuit type Function P74 to P77 General purpose I/O PWM1P1 61 to 64 PWM1M1 Output for Stepping Motor Controller ch. 1 PWM2P1 PWM2M1 P80 to P83 General purpose I/O PWM1P2 67 to 70 PWM1M2...
Page 46 These are power supply (0V) input pins This is the power supply stabilization capacitor pin. It should be connected to a 0.1 μF or more ceramic capacitor. *: Pin function may not be available in some devices of the MB90390 series.
Page 47: Input-Output Circuits
CHAPTER 1 OVERVIEW Input-Output Circuits Table 1.9-1 lists the input-output circuits. ■ Input-output Circuits Table 1.9-1 I/O Circuit Types (1/3) Type Circuit Remarks • Oscillation feedback resistor: 1 MΩ approx. Clock input P-ch N-ch Standby control signal • CMOS Hysteresis input with pull-up resistor (50 kΩ...
Page 48 CHAPTER 1 OVERVIEW Table 1.9-1 I/O Circuit Types (2/3) Type Circuit Remarks • CMOS output • CMOS Hysteresis input • Automotive Hysteresis input Note: The input characteristics may be different for P-ch different pins/devices. Refer to the data sheet. N-ch CMOS Hysteresis Automotive HYS •...
Page 49 CHAPTER 1 OVERVIEW Table 1.9-1 I/O Circuit Types (3/3) Type Circuit Remarks • CMOS high current output • CMOS Hysteresis input • Automotive Hysteresis input P-ch High current N-ch CMOS Hysteresis Automotive HYS • EVA device: CMOS Hysteresis input with pull- down resistor (50 kΩ...
Page 50: Handling Device
CHAPTER 1 OVERVIEW 1.10 Handling Device Special care is required for the following when handling the device: • Preventing latch-up • Treatment of unused pins • Stabilization of power supply voltage • Using external clock • Power supply input pins (V •...
Page 51 V in the vicinity of V and VSS pins of the device. Figure 1.10-2 Power Supply input Pins (V MB90390 Series ● Pull-up/pull-down resistors The MB90390 Series does not support internal pull-up/pull-down resistors option. Use external components where needed.
Page 52 On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
Page 53: Chapter 2 Cpu
CHAPTER 2 This chapter explains the CPU. 2.1 Outline of the CPU 2.2 Memory Space 2.3 Memory Space Map 2.4 Linear Addressing 2.5 Bank Addressing Types 2.6 Multi-byte Data in Memory Space 2.7 Registers 2.8 Register Bank 2.9 Prefix Codes 2.10 Interrupt Disable Instructions 2.11 Precautions for Use of "DIV A, Ri"...
Page 54: Outline Of The Cpu
CHAPTER 2 CPU Outline of the CPU The F MC-16LX CPU core is a 16-bit CPU designed for applications that require high- speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.
Page 55: Memory Space
CHAPTER 2 CPU Memory Space An F MC-16LX CPU has a 16-Mbyte memory space. All data program input and output managed by the F MC-16LX CPU are located in this 16-Mbyte memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. ■...
Page 56 CHAPTER 2 CPU ■ ROM Area ● Vector table area (address: FFFC00 to FFFFFF This area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors. This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address.
Page 57 CHAPTER 2 CPU ■ Address Generation Types The F MC-16LX has the following two addressing modes: ● Linear addressing An entire 24-bit address is specified by an instruction. ● This register Bank addressing. The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction.
Page 58: Memory Space Map
CHAPTER 2 CPU Memory Space Map The memory space of the MB90390 Series is shown in Figure 2.3-1. ■ Memory Space Map The ROM data in the high-order portion of FF-bank can be seen as an image in the higher 00-bank in order to support the small model C compiler.
Page 59 CHAPTER 2 CPU Figure 2.3-1 Memory Space Map MB90394HA/ F394H(A) MB90V390HA/HB MB90V390H F F F F F F F F F F F F F F F F F F ROM (FF bank) ROM (FF bank) ROM (FF bank) F F 0 0 0 0 F F 0 0 0 0 F F 0 0 0 0 F E F F F F...
Page 60: Linear Addressing
CHAPTER 2 CPU Linear Addressing There are two types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32- bit general-purpose register value as the address ■...
Page 61: Bank Addressing Types
CHAPTER 2 CPU Bank Addressing Types In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The following five bank registers are used to specify the banks corresponding to each space: • Program counter bank register (PCB) •...
Page 62 CHAPTER 2 CPU Table 2.5-1 Default Space Default space Addressing mode Program space PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.5-1 shows the physical addresses of each space.
Page 63: Multi-Byte Data In Memory Space
CHAPTER 2 CPU Multi-byte Data in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written.
Page 64: Registers
CHAPTER 2 CPU Registers The F MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture.
Page 65 CHAPTER 2 CPU Figure 2.7-1 Special Registers Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program counter bank register Data bank register User stack bank register System stack bank register Additional data bank register 8bits 16bits 32bits...
Page 66 CHAPTER 2 CPU ■ General-purpose Registers The F MC-16LX general-purpose registers are located from addresses "000180 " to "00037F " (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.7-2.
Page 67: Accumulator (A)
CHAPTER 2 CPU 2.7.1 Accumulator (A) The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data.
Page 68: User Stack Pointer (Usp) And System Stack Pointer (Ssp)
CHAPTER 2 CPU 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution.
Page 69: Processor Status (Ps)
CHAPTER 2 CPU 2.7.3 Processor Status (PS) The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.7-6, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM).
Page 70 CHAPTER 2 CPU ● T: Sticky bit flag: "1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero.
Page 71 CHAPTER 2 CPU ■ Interrupt Level Mask Register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1).
Page 72: Program Counter (Pc)
CHAPTER 2 CPU 2.7.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset.
Page 73: Register Bank
CHAPTER 2 CPU Register Bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers.
Page 74 CHAPTER 2 CPU ● Direct page register (DPR) <Initial value: 01 > DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure 2.8-1. DPR is eight bits long, and is initialized to "01 "...
Page 75: Prefix Codes
CHAPTER 2 CPU Prefix Codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank Select Prefix The memory space used for accessing data is determined for each addressing mode.
Page 76 CHAPTER 2 CPU ● RETI SSB is used regardless of the prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from "000180 "...
Page 77: Interrupt Disable Instructions
CHAPTER 2 CPU 2.10 Interrupt Disable Instructions Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - NCC - AND CCR,#imm8 - ADB - CMR - POPW PS - DTB ■...
Page 78 CHAPTER 2 CPU ■ Consecutive Prefix Codes When competitive prefix codes are placed consecutively, the latter becomes valid. In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. For details, see Figure 2.10-3. Figure 2.10-3 Consecutive Prefix Codes Prefix code •...
Page 79: Precautions For Use Of "Div A, Ri" And "Divw A, Rwi" Instructions
CHAPTER 2 CPU 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Set "00 " in the bank register before using the "DIV A, Ri" and "DIVW A, RWi" instructions. ■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Table 2.11-1 Precautions for Use of "DIV A, Ri"...
Page 80 "DIVW A,RWi" instructions, special compilers and assemblers are available. The special compiler does not generate the instructions in Table 2.11-1. The special assemblers have a function that replaces the instructions in Table 2.11-1 with equivalent instruction strings. For the MB90390 series, use the following types of compilers and assemblers: ●...
Page 81: Chapter 3 Interrupts
CHAPTER 3 INTERRUPTS This chapter explains the functions and operations of the interrupt and extended intelligent I/O service (EI for MB90390 series. 3.1 Outline of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts...
Page 82: Outline Of Interrupts
CHAPTER 3 INTERRUPTS Outline of Interrupts The F MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: • Hardware interrupt: Interrupt processing due to an internal resource event •...
Page 83 CHAPTER 3 INTERRUPTS Figure 3.1-1 Overview of Hardware Interrupts :Processor status Register file :Interrupt enable flag :Interrupt level mask register Microcode :Instruction register Check Comparator B unit :Bus interface unit M C - 1 6 LX . CPU Peripheral Enable FF Interrupt Cause FF controller...
Page 84 CHAPTER 3 INTERRUPTS Figure 3.1-3 Overview of the Extended Intelligent I/O Service (EI Memory space by IOA Peripheral I/O register I/O register ➀ Interrupt request ➂ by ICS ➁ ➂ Interrupt control register Interrupt controller ➀ I/O requests transfer. ➁ The interrupt controller selects the by BAP descriptor.
Page 85: Interrupt Vector
CHAPTER 3 INTERRUPTS Interrupt Vector An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine.
Page 86 CHAPTER 3 INTERRUPTS Table 3.2-1 Interrupt Vectors (2/2) Interrupt control Vector Interrupt Vector Vector Mode register Interrupt cause address request address L address H register bank Number Address FFFFA0 FFFFA1 FFFFA2 INT 23 16-bit Reload Timer 0 Unused 0000B6 ICR06 FFFF9C FFFF9D FFFF9E...
Page 87: Interrupt Control Registers (Icr)
CHAPTER 3 INTERRUPTS Interrupt Control Registers (ICR) The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function. The interrupt control registers have the following three functions: • Setting an interrupt level for corresponding peripherals •...
Page 88 CHAPTER 3 INTERRUPTS Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels Level 0 (Strongest) 6 (Weakest) 7 (No interrupt) [bit11, bit3] ISE (extended intelligent I/O service enable bits) The ISE bit is readable and writable. In response to an interrupt request, EI OS is activated when "1"...
Page 89 CHAPTER 3 INTERRUPTS Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Addresses ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178 [bit13 and bit12, bit5 and bit4] S0 and S1 (extended intelligent I/O service status) S0 and S1 are read-only bits.
Page 90: Interrupt Flow
CHAPTER 3 INTERRUPTS Interrupt Flow Figure 3.4-1 shows the interrupt flow. ■ Interrupt Flow Figure 3.4-1 Interrupt Flow I: Flag in CCR ILM: Level register in CPU IF: Internal resource interrupt request IE: Internal resource interrupt enable flag ISE: EI OS enable flag IL: Internal resource interrupt request level S: Flag in CCR...
Page 91 CHAPTER 3 INTERRUPTS Figure 3.4-2 Register Saving During Interrupt Processing Word (16 bits) "H" SSP (SSP value before interrupt) SSP (SSP value after interrupt) "L"...
Page 92: Hardware Interrupts
CHAPTER 3 INTERRUPTS Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function. ■...
Page 93: Hardware Interrupt Operation
CHAPTER 3 INTERRUPTS 3.5.1 Hardware Interrupt Operation An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU.
Page 94: Occurrence And Release Of Hardware Interrupt
CHAPTER 3 INTERRUPTS 3.5.2 Occurrence and Release of Hardware Interrupt Figure 3.5-1 shows the occurrence and release of hardware interrupt. ■ Occurrence and Release of Hardware Interrupt Figure 3.5-1 Occurrence and Release of Hardware Interrupt :Processor status Register file :Interrupt enable flag :Interrupt level mask register Microcode :Instruction register...
Page 95 CHAPTER 3 INTERRUPTS Table 3.5-1 Compensation Values for Interrupt Processing Cycle Count Address pointed to by the stack pointer Interpolation value [cycles] External 8-bit External even-numbered address External odd-numbered address Internal even-numbered address Internal odd-numbered address...
Page 96: Multiple Interrupts
CHAPTER 3 INTERRUPTS 3.5.3 Multiple interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. For MB90390 Series, this includes the address ranges "00 " to "BF ", ("3100 "...
Page 97: Software Interrupts
CHAPTER 3 INTERRUPTS Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.
Page 98 CHAPTER 3 INTERRUPTS Figure 3.6-1 Occurrence and Release of Software Interrupt ➀ :Processor status Register file :Interrupt enable flag :Stack flag ➁ B unit :Instruction register Microcode B unit :Bus interface unit Fetch Queue M C - 1 6 LX . C P U Save Instruction bus 1.
Page 99: Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPTS Extended Intelligent I/O Service (EI The EI OS function automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such processing, but OS enables data transfer to be performed like DMA (direct memory access). ■...
Page 100 CHAPTER 3 INTERRUPTS Figure 3.7-1 Outline of Extended Intelligent I/O Service Memory space by IOA Peripheral I/O register ••••••••••••••• I/O register ➀ Interrupt request ➂ by ICS ➁ ➂ Interrupt control register Interrupt controller ➀ I/O requests transfer. by BAP ➁...
Page 101: Extended Intelligent I/O Service Descriptor (Isd)
CHAPTER 3 INTERRUPTS 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between "000100 " and "00017F " in built-in RAM, and consists of the following items: • Data transfer control data • Status data •...
Page 102 CHAPTER 3 INTERRUPTS ■ I/O Register Address Pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A00) of the buffer and I/O register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses "000000 "...
Page 103: Ei 2 Os Status Register (Iscs)
CHAPTER 3 INTERRUPTS 3.7.2 OS Status Register (ISCS) This 8-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed.
Page 104 CHAPTER 3 INTERRUPTS [bit0] SE: Control the termination of the extended intelligent I/O service based on resource requests. 0: The extended intelligent I/O service is not terminated by a resource request. 1: The extended intelligent I/O service is terminated by a resource request.
Page 105: Operation Flow Of And Procedure For Using The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPTS Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI Figure 3.8-1 shows the EI OS operation flow. Figure 3.8-2 shows the EI OS use flow. ■ EI OS Operation Flow Figure 3.8-1 EI OS Operation Flow BAP: Buffer address pointer...
Page 106 CHAPTER 3 INTERRUPTS Figure 3.8-2 EI OS Use Flow Processing by CPU Processing by EI OS initialization Normal (Interrupt request) termination AND (ISE = 1) JOB execution Data transfer Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI OS execution time for each flow is described below.
Page 107 CHAPTER 3 INTERRUPTS Table 3.8-2 Data Transfer Compensation Values for Extended EI OS Execution Time Internal access I/O address pointer Internal Buffer address pointer access B: Byte data transfer E: Even address word transfer O: Odd address word transfer Table 3.8-3 Compensation Values for Interrupt Handling Times Address pointed to by the stack pointer Interpolation value [cycles] External 8-bit...
Page 108: Exceptions
Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software.
Page 109: Chapter 4 Delayed Interrupt
CHAPTER 4 DELAYED INTERRUPT This chapter explains the functions and operations of the delayed interrupt. 4.1 Outline of Delayed Interrupt Module 4.2 Delayed Interrupt Register 4.3 Delayed Interrupt Operation...
Page 110: Outline Of Delayed Interrupt Module
CHAPTER 4 DELAYED INTERRUPT Outline of Delayed Interrupt Module The delayed interrupt source module is used to generate interrupts for switching tasks. Using this module, interrupt requests to the F MC-16LX CPU can be issued and canceled by software. ■ Block Diagram of Delayed Interrupt Figure 4.1-1 is a block diagram of the delayed interrupt source module.
Page 111: Delayed Interrupt Register
CHAPTER 4 DELAYED INTERRUPT Delayed Interrupt Register DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. Upon a reset, the request is canceled. ■...
Page 112: Delayed Interrupt Operation
CHAPTER 4 DELAYED INTERRUPT Delayed Interrupt Operation When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. ■...
Page 113: Chapter 5 Clocks
CHAPTER 5 CLOCKS This chapter describes the clocks used by MB90390 series microcontrollers. 5.1 Clocks 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Registers 5.4 Clock Mode 5.5 Oscillation Stabilization Wait Time 5.6 Connection of an Oscillator or an External Clock to the Microcontroller 5.7 Output of the main clock HCLK and HCLKX...
Page 114: Clocks
CHAPTER 5 CLOCKS Clocks The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. This internal clock is called the machine clock. One internal clock cycle is called one machine cycle. Other clocks include a clock generated by source oscillation, called an oscillation clock, and a clock generated by the internal PLL oscillation, called a PLL clock.
Page 115 CHAPTER 5 CLOCKS ● Machine clock (φ) The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock (whose frequency is the source clock frequency divided by 2) and the other six clocks (whose frequencies are multiples of the source clock frequency).
Page 116 CHAPTER 5 CLOCKS Figure 5.1-1 Clock Supply Map Peripheral function Watchdog timer PPG00 to PPG05 8/16-bit PPG PPG10 to PPG15 Clock generation block 8/16-bit PPG RX/TX Time-base timer Pins CAN0 to CAN4 TIN0/TIN1 1 2 3 4 6 8 Pins 16-bit reload PLL multiplier circuit TOUT0/TOUT1...
Page 117: Block Diagram Of The Clock Generation Block
CHAPTER 5 CLOCKS Block Diagram of the Clock Generation Block The clock generation block consists of five blocks: • System clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • Oscillation stabilization wait time selector ■...
Page 118 CHAPTER 5 CLOCKS ● System clock generation circuit The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator attached to it. Alternatively, an external clock can be input to this circuit. ● PLL multiplier circuit The PLL multiplier circuit multiplies the oscillation clock frequency through PLL oscillation and supplies a clock whose frequency is a multiple of the oscillation clock frequency to the CPU clock selector.
Page 119: Clock Selection Registers
CHAPTER 5 CLOCKS Clock Selection Registers This section lists the clock selection registers and describes the function of each register in detail. ■ Clock Selection Registers Figure 5.3-1 shows the clock selection register. Figure 5.3-1 Clock Selection Registers Initial value Address: 0 0 0 0 A 1 (CKSCR)
Page 120: Clock Selection Register (Ckscr)
CHAPTER 5 CLOCKS 5.3.1 Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to switch between the main clock and a PLL clock and is also used to select an oscillation stabilization wait time and a PLL clock multiplier. ■...
Page 121 CHAPTER 5 CLOCKS Table 5.3-1 Clock Selection Register (CKSCR) (1/2) Bit name Function Note: bit15 Reserved Always write "1" to this bit. • This bit indicates whether the main clock or a PLL clock has been selected as the machine clock. MCM: •...
Page 122 CHAPTER 5 CLOCKS Table 5.3-1 Clock Selection Register (CKSCR) (2/2) Bit name Function • This bit specifies whether the main clock or a PLL clock is selected as the machine clock. • When this bit is "0", a PLL clock is selected. When it is 1, the main clock is selected. •...
Page 123: Pll And Special Configuration Control Register (Psccr)
CHAPTER 5 CLOCKS 5.3.2 PLL and Special Configuration Control Register (PSCCR) The PLL and Special Configuration Control Register adds the selection of a PLL clock multiplier. ■ Configuration of the PLL and Special Configuration Control Register (PSCCR) Figure 5.3-3 shows the configuration of the PLL and Special Configuration Control Register (PSCCR). Table 5.3-2 describes the function of each bit of the PLL and Special Configuration Control Register (PSCCR).
Page 124 CHAPTER 5 CLOCKS Table 5.3-2 PLL and Special Configuration Control Register (PSCCR) Bit name Function bit15 • These bits are reserved bits. Reserved: • Always write "0" to these bits. Reserved bit bit9 • Reading these bits always returns "X". •...
Page 125: Clock Mode
CHAPTER 5 CLOCKS Clock Mode Two clock modes are provided: main clock mode and PLL clock mode. ■ Main Clock Mode and PLL Clock Mode ● Main clock mode In main clock mode, a clock whose frequency is the oscillation clock frequency divided by 2 is used as the operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
Page 126 CHAPTER 5 CLOCKS ■ Machine Clock The machine clock may be a PLL clock output from the PLL multiplier circuit or a clock whose frequency is the source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral functions.
Page 127 CHAPTER 5 CLOCKS Writing "0" to the MCS bit End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1, CS0 = 00 End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1, CS0 = 01 End of PLL clock oscillation stabilization wait &...
Page 128: Oscillation Stabilization Wait Time
CHAPTER 5 CLOCKS Oscillation Stabilization Wait Time When the power is turned on or when stop mode is released an oscillation stabilization wait time is required after oscillation begins because there is no oscillation. When switching from the main clock to a PLL clock occurs, an oscillation stabilization wait time is also required after PLL oscillation starts.
Page 129: Connection Of An Oscillator Or An External Clock To The Microcontroller
Connection of an Oscillator or an External Clock to the Microcontroller The MB90390 series microcontroller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the microcontroller.
Page 130 Example of connecting an external clock to the microcontroller As shown in the example in Figure 5.6-2, connect an external clock to pin X0. Pin X1 must be open. Figure 5.6-2 Example of Connecting an External Clock to the Microcontroller MB90390 series open...
Page 131: Output Of The Main Clock Hclk And Hclkx
CHAPTER 5 CLOCKS Output of the main clock HCLK and HCLKX For the control of output of the main clock HCLK and HCLKX, the clock output Enable Register is used. ■ Clock Output Enable Register Figure 5.7-1 Clock Output Enable Register (CKOE) Initial value Address: 0 0 0 0 3 F...
Page 132 CHAPTER 5 CLOCKS...
Page 133: Chapter 6 Clock Modulator
CHAPTER 6 CLOCK MODULATOR This chapter provides an overview of the Clock Modulator and its features. It describes the register structure and operation of the Clock Modulator. Notes: • Do not use frequency modulation with MB90F394H • Do not use CAN message buffer RAM and clock modulation at the same time with MB90F394H, MB90V390H and MB90V390HA.
Page 134: Overview Of Clock Modulator
CHAPTER 6 CLOCK MODULATOR Overview of Clock Modulator This section gives an overview of the Clock Modulator. ■ Overview The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies. The modulator offers two modes: 1) phase modulation mode and 2) frequency modulation mode In both cases the module is fed with an unmodulated reference clock with frequency F0, provided by the PLL circuit.
Page 135: Register Description Of Clock Modulator
CHAPTER 6 CLOCK MODULATOR Register Description of Clock Modulator Clock Modulator has the following two registers. • Clock Modulation Parameter Register • Clock Modulation Control Register ■ Clock Modulator Registers Address: 0035C0 CMPR Parameter Register CMCR Control/Status Register Address: 0035C2...
Page 136: Registers Of Clock Modulator
CHAPTER 6 CLOCK MODULATOR Registers of Clock Modulator This section lists the clock modulator registers and describes the function of each register in detail. ■ Registers of Clock Modulator Figure 6.3-1 Registers of Clock Modulator Address: bit CMPRL (lower) MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 0035C0 Initial value 1 1 1 1 1 1 0 1...
Page 137: Clock Modulator Control Register (Cmcr)
CHAPTER 6 CLOCK MODULATOR 6.3.1 Clock Modulator Control Register (CMCR) The Clock Modulator Control Register (CMCR) has the following functions: • Set the modulator to power down mode • Modulator enable/disable in phase or frequency modulation mode • Indicates the status of the modulator ■...
Page 138 CHAPTER 6 CLOCK MODULATOR ■ Clock Modulator Control Register Contents Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (1/3) Bit name Function Writing "0": Phase modulation disabled (default). Writing "1": Modulator enabled in phase modulation mode, MCU is running with phase modulated clock •...
Page 139 CHAPTER 6 CLOCK MODULATOR Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (2/3) Bit name Function "0": MCU is running with unmodulated or phase modulated clock "1": MCU is running with frequency modulated clock • FMODRUN indicates the status of the modulator output clock in frequency modulation mode (FMOD=1).
Page 140 CHAPTER 6 CLOCK MODULATOR Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (3/3) Bit name Function "0": Frequency modulation disabled. "1": Frequency modulation enabled. Note: Do not set this bit to "1" with MB90F394H. • To enable the modulator in frequency modulation mode, FMOD must be set to "1". •...
Page 141 CHAPTER 6 CLOCK MODULATOR Table 6.3-2 States of the Modulator FMODRUN PMOD FMOD (read only) modulator disabled modulator enabled in phase modulation mode, modulator is running modulator power on, waiting modulator startup time (> 6 μs) modulator enabled in frequency modulation mode, modulator is calibrating, modulation not active modulator is running in frequency modulation mode modulation is active...
Page 142: Clock Modulation Parameter Register (Cmpr)
CHAPTER 6 CLOCK MODULATOR 6.3.2 Clock Modulation Parameter Register (CMPR) The Modulation Parameter Register (CMPR) determines the modulation degree in frequency modulation mode. ■ Modulation Parameter Register Figure 6.3-3 Modulation Parameter Register CMPRL (lower) Address: MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 0035C0 H Initial value 1 1 1 1 1 1 0 1...
Page 143 CHAPTER 6 CLOCK MODULATOR ■ Modulation Parameter Register Contents Table 6.3-3 Function of Each Bit of the Modulation Parameter Register (CMPR) Bit name Function bit15, Undefined bit14 MP13 to MP0: Depending on the PLL frequency the following modulation parameter settings are bit13 to Modulation possible.
Page 144 CHAPTER 6 CLOCK MODULATOR Note: NOT ALL SETTINGS ARE ALLOWED ON EVERY DEVICE! Please consider the actual maximal allowed clock frequency of the MCU (refer to the data sheet). E.g. if the maximal clock frequency of the device is 25MHz, the setting F0=15MHz, resolution=7, moddegree=2 is not allowed, because the maximal occurring frequency in the modulated clock is 28.33 MHz, which is above the allowed 25MHz.
Page 145 CHAPTER 6 CLOCK MODULATOR Table 6.3-4 Modulation Parameter Settings (2/5) ± phase ± phase skew skew (MHz) F0 (MHz) resolution CMPR degree Min/Max (MHz) [periods] [periods] 10.20 28.33 2.73 7.11 0EB2 9.78 32.12 3.13 8.13 10B0 13.31 17.18 0.78 1.86 02FD 12.29 19.24...
Page 146 CHAPTER 6 CLOCK MODULATOR Table 6.3-4 Modulation Parameter Settings (3/5) ± phase ± phase skew skew (MHz) F0 (MHz) resolution CMPR degree Min/Max (MHz) [periods] [periods] 11.35 27.13 3.19 8.63 1874 11.10 28.65 3.45 9.34 1A73 10.86 30.34 3.72 10.06 1C72 10.64 32.25...
Page 147 CHAPTER 6 CLOCK MODULATOR Table 6.3-4 Modulation Parameter Settings (4/5) ± phase ± phase skew skew (MHz) F0 (MHz) resolution CMPR degree Min/Max (MHz) [periods] [periods] 17.11 24.07 1.06 2.88 087C 16.66 25.01 1.33 3.59 0A7B 16.24 26.02 1.59 4.31 0C7A 15.84 27.13...
Page 148 CHAPTER 6 CLOCK MODULATOR Table 6.3-4 Modulation Parameter Settings (5/5) ± phase ± phase skew skew (MHz) F0 (MHz) resolution CMPR degree Min/Max (MHz) [periods] [periods] 18.87 32.95 1.86 5.03 0E79 21.52 27.13 0.39 1.02 02BE 20.38 29.19 0.78 2.03 04BC 19.35 31.59...
Page 149: Application Note Of The Clock Modulator
CHAPTER 6 CLOCK MODULATOR Application Note of the Clock Modulator Startup/stop sequence for phase modulation mode. Startup/stop sequence for frequency modulation mode. Modulation parameter for frequency modulation mode. ■ Recommended Startup Sequence for Phase Modulation Mode start Switch ON PLL Wait PLL lock time (refer to the MCM flag description in the CLOCK chapter of the hardware manual).
Page 150 CHAPTER 6 CLOCK MODULATOR Note: Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the modulator is running. ■ Modulation Parameter for Frequency Modulation Mode It is not possible to recommend a particular modulation parameter setting to achieve a particular reduction in EMI.
Page 151 CHAPTER 6 CLOCK MODULATOR ■ Recommended Settings Table 6.4-1 lists the some example conditions for PLL clock. Table 6.4-1 Some Example Conditions for PLL Clock maximal allowed clock modulator setting MCU clock PLL clock frequency (refer modulation frequency to the data resolution CMPR degree...
Page 152 CHAPTER 6 CLOCK MODULATOR...
Page 153: Chapter 7 Resets
CHAPTER 7 RESETS This chapter describes resets for the MB90390 series microcontrollers. 7.1 Resets 7.2 Reset Cause and Oscillation Stabilization Wait Times 7.3 External Reset Pin 7.4 Reset Operation 7.5 Reset Cause Bits 7.6 Status of Pins in a Reset...
Page 154: Resets
CHAPTER 7 RESETS Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins processing at the address indicated by the reset vector. The four causes of a reset are as follows •...
Page 155 In the MB90390 series the external reset has to be Min 100 μs for wake-up from Main-Time base timer mode and Min 100 μs + Oscillation time of oscillator + 16 machine cycles for wake-up from Stop mode.
Page 156: Reset Cause And Oscillation Stabilization Wait Times
CHAPTER 7 RESETS Reset Cause and Oscillation Stabilization Wait Times The MB90390 series has four reset causes. The oscillation stabilization wait time for a reset depends on the reset cause. ■ Reset Causes and Oscillation Stabilization Wait Times Table 7.2-1 lists the reset causes and oscillation stabilization wait times.
Page 157 CHAPTER 7 RESETS Note: Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several milliseconds, until stabilization at a natural frequency is attained. A proper oscillation stabilization wait time must be set for the particular oscillator used. See Section "5.5 Oscillation Stabilization Wait Time", for details about oscillation stabilization wait times.
Page 158: External Reset Pin
The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an "L" level signal generates an internal reset. For the MB90390 series, resets are generated in synchronization with the CPU operating clock. However, the I/O port pins are affected by the external reset pin (RST pin) in an asynchronous manner.
Page 159: Reset Operation
CHAPTER 7 RESETS Reset Operation When a reset is cleared, the memory locations from which the mode data and the reset vectors are read are selected according to the setting of the mode pins, and a mode fetch is performed. Mode setting data determines the CPU operating mode and the execution start address after a reset operation ends.
Page 160 CHAPTER 7 RESETS ■ Mode Fetch When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from "FFFFDC "...
Page 161: Reset Cause Bits
CHAPTER 7 RESETS Reset Cause Bits A reset cause can be identified by reading the watchdog timer control register (WDTC). ■ Reset Cause Bits As shown in Figure 7.5-1, a flip-flop is associated with each reset cause. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC).
Page 162 CHAPTER 7 RESETS ■ Correspondence between Reset Cause Bits and Reset Causes Figure 7.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See Table 12.1-2 in Section "12.1 Outline of Watchdog Timer", for details.
Page 163 CHAPTER 7 RESETS ● Clearing the reset cause bits The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit corresponding to a reset cause that has already been generated is not cleared even though another reset is generated (a setting of "1"...
Page 164: Status Of Pins In A Reset
CHAPTER 7 RESETS Status of Pins in a Reset This section describes the status of pins when a reset occurs. ■ Status of Pins During a Reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0). ●...
Page 165: Chapter 8 Low-Power Control Circuit
CHAPTER 8 LOW-POWER CONTROL CIRCUIT This chapter explains the functions and operations of the low-power control circuits. 8.1 Overview of Low-Power Consumption Mode 8.2 Block Diagram of the Low-Power Consumption Control Circuit 8.3 Low-Power Consumption Mode Control Register (LPMCR) 8.4 CPU Intermittent Operation Mode 8.5 Standby Mode 8.6 Status Change Diagram 8.7 Status of Pins in Standby Mode and during Reset...
Page 166: Overview Of Low-Power Consumption Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Overview of Low-Power Consumption Mode The MB90390 series has the following CPU operating modes, any of which can be used depending on operating clock selection and clock operation control: • Clock mode (PLL clock mode or main clock mode) •...
Page 167 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Clock Mode ● PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. ● Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions.
Page 168 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ● Stop mode The stop mode cause the oscillation to stop. All functions are inactivated. Note: Because the stop mode turn off the oscillation clock, data can be retained at the lowest power consumption. In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed.
Page 169: Block Diagram Of The Low-Power Consumption Control Circuit
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Block Diagram of the Low-Power Consumption Control Circuit The low-power consumption control circuit consists of the following seven blocks: • CPU intermittent operation selector • Standby control circuit • CPU clock control circuit • Peripheral clock control circuit •...
Page 170 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ● CPU intermittent operation selector This selector selects the number of clock pulses to halt the CPU during the CPU intermittent operation mode. ● Standby control circuit The standby control circuit controls the CPU clock control and the peripheral clock control circuits and turns the low-power consumption mode on and off.
Page 171: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Low-Power Consumption Mode Control Register (LPMCR) This register switches to or releases the low-power consumption mode. This register also sets the number of CPU clock pulses to halt during the CPU intermittent operation mode. ■ Low-power Consumption Mode Control Register (LPMCR) Figure 8.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Page 172 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Table 8.3-1 Function Description of Each Bit of the Low-power Consumption Mode Control Register (LPMCR) Bit name Function • This bit indicates switching to the stop mode. • When "1" is written to this bit, a switch to the stop mode is performed. STP: bit7 •...
Page 173 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Access to the Low-power Consumption Mode Control Register Writing in the low-power consumption mode control register executes a change in the low-power consumption mode (including the stop mode, sleep mode, and time-base timer mode). Only the instructions listed in Table 8.3-2 should be used for this purpose.
Page 174 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Priorities of the STP, SLP, and TMD Bits If the stop mode, sleep mode, and time-base timer mode are requested concurrently, the stop mode request, time-base timer mode request, and sleep mode request are given priorities in this order for processing. Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the...
Page 175: Cpu Intermittent Operation Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT CPU Intermittent Operation Mode This mode is used for intermittent operation of the CPU while external buses and peripheral functions continue to operate at high speeds. The purpose of this mode is to reduce power consumption. ■...
Page 176: Standby Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Standby Mode The standby mode includes the sleep (PLL sleep, main sleep), time-base timer, and stop modes. ■ Operation Status During Standby Mode Table 8.5-1 shows operation statuses during standby mode. Table 8.5-1 Operation Status During Standby Mode Condition Main Machine...
Page 177: Sleep Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT 8.5.1 Sleep Mode This mode causes the CPU operating clock to stop while other components continue to operate. When the low-power consumption mode control register (LPMCR) indicates a switch to a sleep mode, a switch to the PLL sleep mode occurs if the PLL clock mode has been set.
Page 178 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Release of Sleep Mode The low-power consumption control circuit releases sleep modes when a reset is input or an interrupt occurs. ● Return by a reset A sleep mode is initialized to the main clock mode by a reset. ●...
Page 179: Time-Base Timer Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT 8.5.2 Time-base Timer Mode This mode causes all functions, excluding oscillation, the time-base timer, and the clock timer, to stop. In this mode, only the time-base timer and clock timer operate. ■ Switching to the Time-base Timer Mode When "0"...
Page 180 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Release of Time-base Timer Mode The low-power consumption control circuit releases the time-base timer mode when a reset is input or an interrupt occurs. ● Return by a reset The time-base timer mode is initialized to the main clock mode by a reset. Note: The RST signal must be asserted for at least 100 μs in Main-Time-base Timer Mode.
Page 181: Stop Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT 8.5.3 Stop Mode Because this mode causes oscillation to stop and inactivates all functions, data can be retained by the lowest power consumption. ■ Switching to the Stop Mode When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR), switching to the stop mode occurs.
Page 182 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Release of Stop Mode The low-power consumption control circuit releases the stop mode when a reset is input or an interrupt occurs. Because oscillation of the operating clock is halted before returning from the stop mode, the low- power consumption control circuit enters the oscillation stabilization wait state, then releases the stop mode.
Page 183 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Figure 8.5-2 Release of the Stop Mode (External Reset) RST pin Stop mode Oscillating Main clock Oscillation stabilization wait Oscillating Inactive Inactive PLL clock Main clock CPU clock Inactive Reset sequence Execution CPU operation Reset released. Stop mode released.
Page 184: Status Change Diagram
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Status Change Diagram Figure 8.6-1 shows the status change diagram. ■ Status Change Diagram Figure 8.6-1 Status Change Diagram External reset, watchdog timer reset, software reset Power-on Reset Power-on reset MCS=0 Main clock mode PLL clock mode MCS=1 SLP=1 SLP=1...
Page 185 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Operation Status in Each Operating Mode Table 8.6-1 lists the operation status in each operating mode. Table 8.6-1 Operation Status in Each Operating Mode Watch Time-base Clock Operation status Main clock PLL clock Peripheral timer timer source...
Page 186: Status Of Pins In Standby Mode And During Reset
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Status of Pins in Standby Mode and during Reset The status of pins in the standby mode and during reset are described for the single chip mode. ■ Status of Each Pin in the Single Chip Mode Table 8.7-1 lists the status of each pin in the single chip mode.
Page 187: Usage Notes On Low-Power Consumption Mode
CHAPTER 8 LOW-POWER CONTROL CIRCUIT Usage Notes on Low-Power Consumption Mode Note the following four items when using the low-power consumption mode: • Switching to a standby mode and interrupt • Notes on the transition to standby mode • Release of a standby mode by an interrupt •...
Page 188 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Note: If the CPU does not branch to the interrupt processing routine immediately after a return, action such as interrupt disabling must be taken before a standby mode is set. ■ Release of the Stop Mode The stop mode can be released by an input that has been set as an external interrupt input cause before the system enters the stop mode.
Page 189 CHAPTER 8 LOW-POWER CONTROL CIRCUIT ■ Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode ● To access the low-power consumption mode control register (LPMCR) with assembler language To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 8.3-2.
Page 190 CHAPTER 8 LOW-POWER CONTROL CIRCUIT Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I:_IO_LPMCR, #H’98 /* Set LPMCR STP bit to "1" */ JMP $+3 /* Jump to next instruction */;...
Page 191: Chapter 9 Memory Access Modes
CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. 9.1 Outline of Memory Access Modes 9.2 Mode Pins of Memory Access Mode 9.3 Mode Data of Memory Access Mode...
Page 192: Outline Of Memory Access Modes
In user applications, please use the MB90390 Series in the single chip mode. To set the MB90390 Series into the single chip mode, the mode inputs (MD2 to MD0) should be "011 " and the most significant two bits of the mode data (M1 and M0) should be "00 ".
Page 193: Mode Pins Of Memory Access Mode
CHAPTER 9 MEMORY ACCESS MODES Mode Pins of Memory Access Mode Table 9.2-1 describes the operations specified by combinations of the MD2 to MD0 external pins. ■ Mode Pins Table 9.2-1 Mode Pins and Modes Mode pin setting Reset vector External data Mode name Remarks...
Page 194: Mode Data Of Memory Access Mode
CHAPTER 9 MEMORY ACCESS MODES Mode Data of Memory Access Mode Mode data is stored at "FFFFDF " of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device.
Page 195 CHAPTER 9 MEMORY ACCESS MODES Figure 9.3-2 shows the access areas and physical addresses in each bus mode. Figure 9.3-2 Access Areas and Physical Addresses in Each Bus Mode FFFFFF ROM (FF bank) FF0000 FEFFFF ROM (FE bank) FE0000 FDFFFF ROM (FD bank) FD0000 FCFFFF...
Page 196 Table 9.3-2 Sample Recommended Setting of Mode Pins and Mode Data Sample setting Single chip Note: For the MB90390 series devices with Flash memory, the mode data have predetermined values by the hard-wired logic. For more information, refer to Section "28.9 Reset Vector Address in Flash Memory".
Page 197: Chapter 10 I/O Ports
CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. 10.1 I/O Ports 10.2 I/O Port Registers...
Page 198: I/O Ports
CHAPTER 10 I/O PORTS 10.1 I/O Ports Each pin of the ports can be specified as input or output using the direction register if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read.
Page 199: I/O Port Registers
CHAPTER 10 I/O PORTS 10.2 I/O Port Registers There are four types of I/O port registers: • Port data register (PDR0 to PDRB) • Port direction register (DDR0 to DDRB) • Analog input enable register (ADER) • Input level select register (ILSR) ■...
Page 200: Port Data Register
CHAPTER 10 I/O PORTS 10.2.1 Port Data Register Note that Read/Write for I/O ports differ from Read/Write for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch. •...
Page 201 CHAPTER 10 I/O PORTS ■ Reading the Port Data Register When a Port Data register is read, the value depends on the corresponding bit in the Data Direction Register and on the current status of the resource that is connected to the same pin (if applicable). The following cases are possible: DDR value Resource...
Page 202: Data Direction Register
CHAPTER 10 I/O PORTS 10.2.2 Data Direction Register When a pin is used as a port, the corresponding pin is controlled as described below: 0: Input mode 1: Output mode ■ Data Direction Register Figure 10.2-3 shows the data direction registers. Figure 10.2-3 Data Direction Registers DDR0 Initial value...
Page 203: Analog Input Enable Register
CHAPTER 10 I/O PORTS 10.2.3 Analog Input Enable Register This register controls the port 6 and port B pins as described below: 0: Port input/output mode 1: Analog input mode If an external pin is used as an analog input for the A/D converter, the corresponding bit should be set to "1".
Page 204: Input Level Select Register
CHAPTER 10 I/O PORTS 10.2.4 Input Level Select Register The Input Level Select Register allows to switch from Automotive Hysteresis input levels to CMOS Hysteresis input levels. ■ Input Level Select Register The input level select register (ILSR) is located on addresses "0E "...
Page 205: Chapter 11 Time-Base Timer
CHAPTER 11 TIME-BASE TIMER This chapter explains the functions and operations of the time-base timer. 11.1 Outline of Time-base Timer 11.2 Time-base Timer Control Register 11.3 Operations of Time-base Timer...
Page 206: Outline Of Time-Base Timer
CHAPTER 11 TIME-BASE TIMER 11.1 Outline of Time-base Timer The time-base timer consists of an 18-bit time-base counter and a control register. The 18-bit time-base counter divides the system clock. The time-base timer issues interrupts at specified intervals based on carry signals of the time-base counter. ■...
Page 207: Time-Base Timer Control Register
CHAPTER 11 TIME-BASE TIMER 11.2 Time-base Timer Control Register The time-base timer control register controls interrupts of the time-base timer and can clear the time-base counter. ■ Time-base Timer Control Register (TBTC) Figure 11.2-1 Configuration of the Time-base Timer Control Register (TBTC) Initial value Address: 1 X X 0 0 1 0 0...
Page 208 CHAPTER 11 TIME-BASE TIMER Table 11.2-1 Function Description of Each Bit of the Time-base Timer Control Register Bit name Function This is a reserved bit. When writing data to the TBTC register ensure that "1" is bit15 Reserved bit written to this bit. −...
Page 209: Operations Of Time-Base Timer
CHAPTER 11 TIME-BASE TIMER 11.3 Operations of Time-base Timer The time-base timer functions as a watch-dog timer clock source, timer for oscillation stabilization wait time, and interval timer for generating interrupts at specified intervals. ■ Time-base Counter The time-base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two.
Page 210 CHAPTER 11 TIME-BASE TIMER...
Page 211: Chapter 12 Watchdog Timer
CHAPTER 12 WATCHDOG TIMER This chapter explains the functions and operations of the watchdog timer. 12.1 Outline of Watchdog Timer 12.2 Watchdog Timer Operation...
Page 212: Outline Of Watchdog Timer
CHAPTER 12 WATCHDOG TIMER 12.1 Outline of Watchdog Timer The watchdog timer consists of a two-bit watchdog counter, control register, and watchdog reset controller. The two-bit watchdog counter uses the carry signals of an 18-bit time-base counter as a clock source. ■...
Page 213 CHAPTER 12 WATCHDOG TIMER ■ Watchdog Timer Control Register (WDTC) Figure 12.1-2 Configuration of Watchdog Timer Control Register (WDTC) Initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 XXXXX111 Address : PONR WRST ERST SRST 0000A8 R : Read only W : Write only X : Undefined value - : Undefined...
Page 214 CHAPTER 12 WATCHDOG TIMER [bit1, bit0] WT1, WT0 These bits are used to select the watchdog timer interval. Only the data items written during watchdog timer activation are valid. Data items that are written outside watchdog timer activation are ignored. Table 12.1-2 lists the interval settings.
Page 215: Watchdog Timer Operation
CHAPTER 12 WATCHDOG TIMER 12.2 Watchdog Timer Operation The watchdog timer function enables detection of program surge. If the watchdog timer is not accessed within the specified time due to, for example, a program surge, the watchdog timer resets the system. ■...
Page 216 CHAPTER 12 WATCHDOG TIMER ■ Activation The watchdog timer is activated by writing "0" to the WTE bit of the WDTC register while the watchdog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watchdog timer reset interval. Only the interval setting specified during activation is valid.
Page 217 CHAPTER 12 WATCHDOG TIMER ■ Watchdog Timer Behavior at Reset When any kind of reset is asserted, the watchdog timer is deactivated and remains inactive after reset is released (Table 12.2-1). Table 12.2-1 : Watchdog Timer Clear and Stop Conditions Mode WDTC Time-base...
Page 218 CHAPTER 12 WATCHDOG TIMER...
Page 219 CHAPTER 13 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O timer. 13.1 Outline of 16-Bit I/O Timer 13.2 16-Bit I/O Timer Registers 13.3 16-bit Free-run Timer 13.4 Output Compare 13.5 Input Capture...
Page 220: Chapter 13 16-Bit I/O Timer
13.1 Outline of 16-Bit I/O Timer The MB90390 Series contains two 16-bit free-run timer modules, four output compare modules, and three input capture modules and supports six input channels and eight output channels. The following sections describe the 16-bit free-run timer, Output Compare and Input Capture.
Page 221 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture (2 Channels per One Module) The three input capture modules consist of two 16-bit capture registers and control registers each corresponding to two independent external input pins. Input Capture 0 (channels IN0 and IN1) is assigned to Free-run Timer 0 and Input Capture 1 and 2 (channels IN2, IN3, IN4 and IN5) are assigned to Free-run Timer 1.
Page 222: 16-Bit I/O Timer Registers
CHAPTER 13 16-BIT I/O TIMER 13.2 16-Bit I/O Timer Registers The 16-bit I/O timer has the following three registers: • 16-bit free-run timer register • 16-bit output compare register • 16-bit input capture register ■ 16-bit Free-run Timer 0 and 1 Address: 00352C TCDT0...
Page 223 CHAPTER 13 16-BIT I/O TIMER ■ 16-bit Input Capture Address: 003520 H IPCP0/IPCP1 Capture register 0/1 003522 H 003524 H Capture register 2/3 IPCP2/IPCP3 003526 H 003528 H IPCP4/IPCP5 Capture register 4/5 00352A H 000054 H ICS0/ICS1 Control register 0/1 000055 H Control register 2/3 ICS2/ICS3...
Page 224: 16-Bit Free-Run Timer
• The counter value can be initialized upon a match with compare register 0 (free-run timer 0) or compare register 4 (free-run timer 1), depending on the mode. • Two separate timers are available on MB90390 series. ■ 16-bit Free-run Timer Block Diagram Figure 13.3-1 16-bit Free-run Timer Block Diagram...
Page 225: Data Register
CHAPTER 13 16-BIT I/O TIMER 13.3.1 Data Register The data register can read the count value of the 16-bit free-run timer. The counter value is cleared to "0000 " upon a reset. The timer value can be set by writing a value to this register.
Page 226: Control Status Register
CHAPTER 13 16-BIT I/O TIMER 13.3.2 Control Status Register The control status register sets the operation mode of the 16-bit free-run timer, starts and stops the 16-bit free-run timer, and controls interrupts. ■ Control Status Register of Free-run Timer (Lower) Figure 13.3-3 Control Status Register of Free-run Timer (TCCSL0/TCCSL1) TCCSL0/TCCSL1 Address:...
Page 227 CHAPTER 13 16-BIT I/O TIMER Table 13.3-1 Control Status Register of Free-run Timer (Lower) Bit name Function • This bit is the interrupt request flag bit and clear bit IVF: • Writing "0": A possible interrupt is cleared. bit7 Interrupt request flag •...
Page 228 CHAPTER 13 16-BIT I/O TIMER ■ Control Status Register of Free-run Timer (Upper) Figure 13.3-4 Control Status Register of Free-run Timer (TCCSH0/1) TCCSH0/TCCSH1 Address: 00352F Initial value ECKE 0 x x x x x x x 00353F External clock enable ECKE Internal time clock Readable and writable...
Page 229: 16-Bit Free-Run Timer Operation
CHAPTER 13 16-BIT I/O TIMER 13.3.3 16-bit Free-run Timer Operation The 16-bit free-run timer starts counting from counter value "0000 " after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations.
Page 230 CHAPTER 13 16-BIT I/O TIMER ■ Clearing the Counter Upon a Match with Output Compare Register 0 (4) Figure 13.3-6 Clearing the Counter Upon a Match with Output Compare Register 0 (4) Counter value FFFF Match Match BFFF 7FFF 3FFF Time 0000 Reset...
Page 231: Output Compare
■ Output Compare • Four separate Output Compare Modules are available on MB90390 series. • For each module, two compare registers exist which can be used independently. Depending on the mode setting, the two compare registers can be used to control pin outputs.
Page 232: Output Compare Register
CHAPTER 13 16-BIT I/O TIMER 13.4.1 Output Compare Register These 16-bit compare registers are compared with the 16-bit free-run timer. Since the initial register values are undefined, set appropriate value before enabling the operation. These registers must be accessed by the word access instructions. When the value of the register matches that of the 16-bit free-run timer, a compare signal is generated and the output compare interrupt flag is set.
Page 233: Control Status Register Of Output Compare
CHAPTER 13 16-BIT I/O TIMER 13.4.2 Control Status Register of Output Compare The control status register sets the operation mode of output compare, starts and stops output compare, controls interrupts, and sets the external output pins. ■ Control Status Register of Output Compare (Lower) Figure 13.4-3 Control Status Register of Output Compare (OCS0/OCS2/OCS4/OCS6) OCS0 OCS2...
Page 234 CHAPTER 13 16-BIT I/O TIMER Table 13.4-1 Control Status Register of Output Compare (Lower) Bit name Function bit7 ICPm • These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register value matches the 16-bit free-run timer value. While the interrupt request bits (ICEm and ICEn) are enabled, an output compare interrupt occurs when the ICPm and ICPn bits are set.
Page 235 CHAPTER 13 16-BIT I/O TIMER ■ Control Status Register of Output Compare (Upper) Figure 13.4-4 Control Status Register of Output Compare (OCS1/OCS3/OCS5/OCS7) OCS1 OCS3 Address: OCS5 OCS7 000059 CMOD1 CMOD0 OTEm OTEn OTDm OTDn Initial value 00005B 0 X X 0 0 0 0 0 00005D R/W R/W R/W R/W...
Page 236 CHAPTER 13 16-BIT I/O TIMER Table 13.4-2 Control Status Register of Output Compare (Upper) Bit name Function These bits define the operation mode for the pin output value. Depending on the CMOD0, bit15, bit12 defined mode, the level is reversed upon a match with different compare registers. See CMOD1 Table 13.4-3 and Section "13.4.3 16-bit Output Compare Operation"...
Page 237 CHAPTER 13 16-BIT I/O TIMER Table 13.4-3 Function of CMOD1 and 0 Bits Pin output value reversed upon match with register no. OCS1 Register OCCPx CMOD1 CMOD0 OUT0 OUT1 OCS3 Register OCCPx CMOD1 CMOD0 OUT2 OUT3 0/2/3 OCS5 Register OCCPx CMOD1 CMOD0 OUT4...
Page 238: 16-Bit Output Compare Operation
CHAPTER 13 16-BIT I/O TIMER 13.4.3 16-bit Output Compare Operation In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16- bit free-run timer value. The CMOD0 and CMOD1 bits can be used to define the corresponding compare registers for each pin.
Page 239 CHAPTER 13 16-BIT I/O TIMER ■ Sample Output Waveform with Two Compare Registers when CMOD[1:0] = 01 When CMOD[1:0] = 01 , the output level of the pin corresponding to compare register 0 (2) is reversed upon every match with the register value. This is identical to the behavior for CMOD[1:0] = 00 .
Page 240 CHAPTER 13 16-BIT I/O TIMER ■ Sample Output Waveform when CMOD[1:0] = 10 The operation mode defined by CMOD[1:0] = 10 is intended for the use of three pulse width modulated signals for each free-run timer instead of two. If this mode is set to OCU module 1, a match of the timer value with compare register 0 reverses both OUT2 and OUT3.
Page 241 CHAPTER 13 16-BIT I/O TIMER ■ Sample Output Waveform when CMOD[1:0] = 11 When CMOD[1:0] = 11 , the output level of the OUT3 (OUT7) pin is reversed by the compare registers 0, 2 or 3 (4, 6 or 7). For the pin OUT1 (OUT5), this setting is identical to CMOD[1:0] = 01 (see also Table 13.4-3).
Page 242 CHAPTER 13 16-BIT I/O TIMER ■ Output Compare Timing In output compare operation, a compare match signal is generated when the free-run timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter timing.
Page 243: Input Capture
CHAPTER 13 16-BIT I/O TIMER 13.5 Input Capture Input capture detects a rising or falling edge or both edges of an external input signal and stores a 16-bit free-run timer value at that time in a register. In addition, input capture can generate an interrupt upon detection of an edge.
Page 244: Input Capture Register Details
CHAPTER 13 16-BIT I/O TIMER 13.5.1 Input Capture Register Details Input capture has the three registers listed. These registers store a value from the 16-bit free-run timer when a valid edge of the corresponding external pin input waveform is detected. (The registers must be accessed in word mode. No values can be written to the registers.) •...
Page 245 CHAPTER 13 16-BIT I/O TIMER ■ Control Status Register Figure 13.5-3 Control Status Register (ICS) ICS01 Address: 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 Initial value 000054 ICS23 0 0 0 0 0 0 0 0 000055 ICS45 000056 R/W R/W R/W R/W R/W R/W R/W bit9/bit1...
Page 246 CHAPTER 13 16-BIT I/O TIMER Table 13.5-2 Input Capture Control Status Register Bits (Upper and Lower) Bit name Function • This bit is used as interrupt request flag for input capture n and m • "1" is set to this bit upon detection of a valid edge of an external input pin. ICPn+1/3: •...
Page 247 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture Edge Register (ICE01, ICE23, ICE45) Figure 13.5-4 Input Capture Edge Register (ICE) Initial value Address: 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 X X X X X 0 X X 0035C9 * ICE01 and ICE45 ("X"...
Page 248 CHAPTER 13 16-BIT I/O TIMER Table 13.5-3 Input Capture Edge Register Bits (Upper and Lower) Bit name Function bit15 to bit11, − Undefined bit7 to bit3 IUCE1/IUCE5: • This bit selects the capture source for Input Capture Unit 1 and 5, and is used by Input Capture to UART3-LIN-Operation bit10...
Page 249: 16-Bit Input Capture Operation
CHAPTER 13 16-BIT I/O TIMER 13.5.2 16-bit Input Capture Operation In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified edge, fetching the 16-bit free-run timer value and writing it to the capture register. ■...
Page 250 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture Input Timing ● Capture timing for input signals Figure 13.5-6 Capture Timing for Input Signals φ Counter value Input capture input Valid edge Capture signal Capture register Interrupt...
Page 251: Chapter 14 16-Bit Reload Timer (With Event Count Function)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) This chapter explains the functions and operations of the 16-bit reload timer (with the event count function). 14.1 Outline of 16-Bit Reload Timer (with Event Count Function) 14.2 16-Bit Reload Timer (with Event Count Function) 14.3 Internal Clock and External Clock Operations of 16-bit Reload Timer 14.4 Underflow Operation of 16-bit Reload Timer...
Page 252: Outline Of 16-Bit Reload Timer (With Event Count Function)
The input pin (TIN) is used for event input in event count mode, and can be used for trigger input or gate input in internal clock mode. The MB90390 Series has two 16-bit reload timers. ■ Intelligent I/O Service (EI...
Page 253 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ■ Block Diagram of 16-bit Reload Timer Figure 14.1-1 shows a block diagram of the 16-bit reload timer. Figure 14.1-1 Block Diagram of 16-bit Reload Timer 16-bit reload register Reload RELD 16-bit down-counter OUTE OUTL...
Page 254: 16-Bit Reload Timer (With Event Count Function)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.2 16-Bit Reload Timer (with Event Count Function) The 16-bit reload timer has the following two types of registers: • Timer control register (TMCSR) • 16-bit timer register (TMR)/16-bit reload register (TMRLR) ■...
Page 255: Timer Control Status Register (Tmcsr)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.2.1 Timer Control Status Register (TMCSR) Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other than UF, CNTE, and TRG when CNTE = 0. ■ Register Layout of Timer Control Register (TMCSR) TMCSR0/TMCSR1 (upper) Address: 000051...
Page 256 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) [bit9, bit8, bit7] MOD2, MOD1, MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = 0, the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds.
Page 257 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) [bit6] OUTE Output enable bit. The TOT pin functions as a general-purpose port when this bit is "0" and as the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode, TOT outputs a square waveform that indicates that counting is in progress.
Page 258: Register Layout Of 16-Bit Timer Register (Tmr)/16-Bit Reload Register (Tmrlr)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) • TMR contents (for reading) Reading this register reads the count value of the 16-bit timer. The initial value is undefined.
Page 259: Internal Clock And External Clock Operations Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.3 Internal Clock and External Clock Operations of 16-bit Reload Timer The machine clock divided by 2 , or 2 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting.
Page 260 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode) The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source.
Page 261: Underflow Operation Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.4 Underflow Operation of 16-bit Reload Timer An underflow is defined for this timer as the time when the counter value changes from "0000 " to "FFFF ". Therefore, an underflow occurs after (reload register setting + 1) counts.
Page 262: Output Pin Functions Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.5 Output Pin Functions of 16-bit Reload Timer In reload mode, the TOT pin performs toggle output (inverts at each underflow). In one- shot mode, the TOT pin functions as a pulse output that shows a particular level while the count is in progress.
Page 263: Counter Operation State
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 14.6 Counter Operation State The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Available states are: CNTE = 0 and WAIT = 1 (STOP state), CNTE = 1 and WAIT = 1 (WAIT state for trigger), and CNTE = 1 and WAIT = 0 (RUN state).
Page 264 CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
Page 265: Chapter 15 Watch Timer
CHAPTER 15 WATCH TIMER This chapter explains the functions and operations of the Watch Timer. 15.1 Outline of Watch Timer 15.2 Watch Timer Registers...
Page 266: Outline Of Watch Timer
CHAPTER 15 WATCH TIMER 15.1 Outline of Watch Timer The Watch Timer consists of the Timer Control register, Sub-second register, Second/ Minute/Hour registers, 1/2 clock divider, 22-bit prescaler and Second/Minute/Hour counters. The oscillation frequency of the MCU is assumed to be at 4MHz or 5MHz for the aimed operation of the Watch Timer.
Page 267: Watch Timer Registers
CHAPTER 15 WATCH TIMER 15.2 Watch Timer Registers The Watch Timer has the following five types of registers: • Timer control register (WTCR) • Subsecond register (WTBR) • Second register (WTSR) • Minute register (WTMR) • Hour register (WTHR) ■ Watch Timer Registers Figure 15.2-1 Watch Timer Registers Timer control register Address:...
Page 268: Timer Control Register
CHAPTER 15 WATCH TIMER 15.2.1 Timer Control Register The timer control register starts and stops the Watch Timer, controls interrupts, and sets the external output pins. ■ Timer Control Register (Lower) Figure 15.2-2 Configuration of the Watch Timer Control Register (Lower) WTCR Address: 000060...
Page 269 CHAPTER 15 WATCH TIMER Table 15.2-1 Timer Control Register (Lower) Bit name Function bit7 to Reserved These are reserved bits. Always write "0" to these bits. bit5 bit4, − Undefined bit3 The UPDT bit is prepared for modifying the Second/Minute/Hour counter values. To modify the counter values, write the modified data in the Second/Minute/Hour registers.
Page 270 CHAPTER 15 WATCH TIMER ■ Timer Control Register (Upper) Figure 15.2-3 Configuration of the Timer Control Register (Upper) WTCR Address: 000061 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W bit8 Interrupt request bit 0 INT0 write read...
Page 271 CHAPTER 15 WATCH TIMER Table 15.2-2 Timer Control Register (Upper) Bit name Function INTE3 to INTE0 are the interrupt flags. They are set when the second counter, minute counter and hour counter overflow respectively. If a INT bit is set while the corresponding INTE bit is "1", the Watch Timer signals an interrupt.
Page 272: Sub-Second Registers
CHAPTER 15 WATCH TIMER 15.2.2 Sub-second Registers The sub-second register stores a reload value for the 22-bit prescaler that divides the oscillation clock. The reload value is usually set so that the 22-bit prescaler will output exactly within a one-second cycle. This register is not initialized by reset, but 22-bit prescaler is initialized by reset.
Page 273: Second/Minute/Hour Registers
CHAPTER 15 WATCH TIMER 15.2.3 Second/Minute/Hour Registers The Second/Minute/Hour registers stores the time information. It is a binary representation of the second, minute and hour. Reading these registers simply returns the counter values. These registers are write accessible however, the written data is loaded in the counters after the UPDT bit is set to "1".
Page 274 CHAPTER 15 WATCH TIMER...
Page 275: Chapter 16 8/16-Bit Ppg
CHAPTER 16 8/16-BIT PPG This chapter explains the 8/16-bit PPG and explains its functions. 16.1 Outline of 8/16-bit PPG 16.2 Block Diagram of 8/16-bit PPG 16.3 8/16-bit PPG Registers 16.4 Operations of 8/16-bit PPG 16.5 Selecting a Count Clock for 8/16-bit PPG 16.6 Controlling Pin Output of 8/16-bit PPG Pulses 16.7 8/16-bit PPG Interrupts 16.8 Initial Values of 8/16-bit PPG Hardware...
Page 276: Outline Of 8/16-Bit Ppg
Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module can be used as a D/A converter. The MB90390 Series contains six PPG’s. The following sections only describe the functionality of the PPG0/PPG1. The remaining PPG’s have the identical function and the register addresses should be found in the I/O map.
Page 277 CHAPTER 16 8/16-BIT PPG Figure 16.1-1 Relationship between PPG Modules and External Pins PPG00 PPG0 / PPG1 PPG10 PPG01 PPG2 / PPG3 PPG11 PPG02 PPG4 / PPG5 Internal External PPG12 Modules Pins PPG03 PPG6 / PPG7 PPG13 PPG04 PPG8 / PPG9 PPG14 PPG05 PPGA / PPGB...
Page 278: Block Diagram Of 8/16-Bit Ppg
Peripheral clock 4-division Peripheral clock 2-division Peripheral clock PPG00 Output latch Clear Invert PEN0 In MB90390 series, this IRQ signal merged with the Channel1 IRQ signal by OR logic. PCNT Count clock (down counter) selection Reload Time-base counter output, ch.1 borrow 512-division of main clock "L"/"H"...
Page 279 Peripheral clock 4-division Peripheral clock 2-division Peripheral clock PPG10 Output latch Clear Invert PEN1 In MB90390 series, this IRQ signal merged with the Channel0 IRQ signal by OR logic. PCNT (down counter) ch.0 borrow Reload Time-base counter output, 512-division of main clock "L"/"H"...
Page 280 CHAPTER 16 8/16-BIT PPG ● Details of pins in block diagram Table 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 16.2-1 Pins and Interrupt Request Numbers in Block Diagram Channel Output Pin Interrupt Request Number PPG0 P56/PPG00...
Page 281 CHAPTER 16 8/16-BIT PPG ● Reload register L/H selector This selector detects the current pin output level to select which register value, Low reload register (PRLL0) or High reload register (PRLH0), should be reloaded to the PPG0 down counter. ● Count clock selector This selector selects the count clock to be input to the PPG0 down counter from five frequency-divided clocks of the machine clock or the frequency-divided clocks of the time-base timer.
Page 282: 8/16-Bit Ppg Registers
CHAPTER 16 8/16-BIT PPG 16.3 8/16-bit PPG Registers The 8/16-bit PPG has the following five types of registers: • PPGC0 (PPGC2, PPGC4, PPGC6, PPGC8, PPGCA) Operation Mode Control Register • PPGC1 (PPGC3, PPGC5, PPGC7, PPGC9, PPGCB) Operation Mode Control Register •...
Page 283: Ppg0 Operation Mode Control Register (Ppgc0)
CHAPTER 16 8/16-BIT PPG 16.3.1 PPG0 Operation Mode Control Register (PPGC0) PPGC0 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG0 Operation Mode Control Register (PPGC0) Figure 16.3-1 Configuration of the PPG0 Operation Mode Control Register PPG0 operation mode control register Address:...
Page 284 Operation enable bit disabled but output is enabled (bit5), a "L" level is maintained at the output. PE00: When set to "1", this bit enables the pulse output. For MB90390 Series, the pulse signal is bit5 PPG00 pin output output to the "PPG00" external pin. When disabled, the pin can be used as general- enable bit purpose port.
Page 285: Ppg1 Operation Mode Control Register (Ppgc1)
CHAPTER 16 8/16-BIT PPG 16.3.2 PPG1 Operation Mode Control Register (PPGC1) PPGC1 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. ■ PPG1 Operation Mode Control Register (PPGC1) Figure 16.3-2 Configuration of the PPG1 Operation Mode Control Register PPG1 operation mode control register...
Page 286 Operation enable bit is disabled but output is enabled (bit13), a "L" level is maintained at the output. PE10: When set to "1", this bit enables the pulse output. For MB90390 Series, the pulse bit13 PPG10 pin output signal is output to the "PPG10" external pin. When disabled, the pin can be used as enable bit general-purpose port.
Page 287: Ppg0/1 Clock Select Register (Ppg01)
CHAPTER 16 8/16-BIT PPG 16.3.3 PPG0/1 Clock Select Register (PPG01) The PPG0/1 Clock Select Register (PPG01) is an 8-bit control register that controls the counter clock of the 8/16-bit PPG. ■ PPG0/1 Clock Select Register (PPG01) Figure 16.3-3 Configuration of the PPG0/1 Clock Select Register (PPG01) PPG0/1 Clock Select Registers PPG01 Address:...
Page 288 CHAPTER 16 8/16-BIT PPG Table 16.3-3 Bit Function Description of the Clock Select Register (PPG01) Bit name Function These bits select the operation clock for the down counter of Channel 1 as described below. Note: In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch.1 PPG operates in response to a counter clock from ch.0.
Page 289: Reload Register (Prll/Prlh)
CHAPTER 16 8/16-BIT PPG 16.3.4 Reload Register (PRLL/PRLH) The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the PCNT down counters. The PRLL and PRLH registers are readable and writable. ■ Reload Register (PRLL/PRLH) Reload register H Address: ch.0 003501 ch.1 003503 ch.2 003505...
Page 290: Operations Of 8/16-Bit Ppg
CHAPTER 16 8/16-BIT PPG 16.4 Operations of 8/16-bit PPG One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. ■...
Page 291 CHAPTER 16 8/16-BIT PPG ■ 8/16-bit PPG Output Operation In this block, the ch.0 PPG is activated to start counting when "1" is written to bit7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch.1 PPG is activated to start counting when "1" is written to bit15 (PEN1) of the PPGC1 register.
Page 292: Selecting A Count Clock For 8/16-Bit Ppg
CHAPTER 16 8/16-BIT PPG 16.5 Selecting a Count Clock for 8/16-bit PPG The count clock used for the operation is supplied from the peripheral clock or the time- base timer. The count clock can be selected from six choices. ■ Selecting a Count Clock for 8/16-bit PPG Select ch.0 clock at bit4 to bit2 (PCM2 to PCM0) of the PPG01 register, and ch.1 clock at bit7 to bit5 (PCS2 to PCS0) of the PPG01 register.
Page 293: Controlling Pin Output Of 8/16-Bit Ppg Pulses
CHAPTER 16 8/16-BIT PPG 16.6 Controlling Pin Output of 8/16-bit PPG Pulses The pulses generated by this module can be output from external pins PPG00 and PPG10. ■ Controlling Pin Output of 8/16-bit PPG Pulses To output the pulses from an external pin, write "1" to the bit corresponding to each pin (PPGC0: PE00, PPGC1: PE10).
Page 294: 8/16-Bit Ppg Interrupts
CHAPTER 16 8/16-BIT PPG 16.7 8/16-bit PPG Interrupts For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and a borrow occurs. ■ 8/16-bit PPG Interrupts In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter.
Page 295: Initial Values Of 8/16-Bit Ppg Hardware
CHAPTER 16 8/16-BIT PPG 16.8 Initial Values of 8/16-bit PPG Hardware The hardware components of this block are initialized to the following values when reset: ■ Initial Values of 8/16-bit PPG Hardware ● Registers PPGC0 → 0X000XX1 • PPGC1 → 0X000001 •...
Page 296 CHAPTER 16 8/16-BIT PPG Assume that PRLL is updated from A to C before (1) in the time chart above, and PRLH is updated from B to D after (1). Since the PRL values at (1) are PRLL=C and PRLH=B, a pulse of "L" side count value C and "H"...
Page 297: Chapter 17 Dtp/External Interrupts
CHAPTER 17 DTP/EXTERNAL INTERRUPTS This chapter explains the functions and operations of the DTP/external interrupts. 17.1 Outline of DTP/External Interrupts 17.2 DTP/External Interrupt Registers 17.3 Operations of DTP/External Interrupts 17.4 Switching between External Interrupt and DTP Requests 17.5 Notes on Using DTP/External Interrupts...
Page 298: Outline Of Dtp/External Interrupts
"H", "L", rising edge, and falling edge. For the MB90390 Series, the external bus interface is not supported. Therefore the DTP/External Interrupt can not serve as the data transfer peripheral. It can be only used as the External Interrupt.
Page 299: Dtp/External Interrupt Registers
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.2 DTP/External Interrupt Registers The DTP/external interrupts has the following three types of registers: • Interrupt/DTP enable register (ENIR: Interrupt request enable register) • Interrupt/DTP flag (EIRR: External interrupt request register) • Request level setting register (ELVR: External level register) ■...
Page 300 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Note: If multiple external interrupt request outputs are enabled (ENIR: EN3 to EN0=1), only the bits for which the CPU accepts an interrupt (bits for which "1" was set in ER3 to ER0) are cleared. No other bits must be cleared unconditionally.
Page 301: Operations Of Dtp/External Interrupts
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3 Operations of DTP/External Interrupts When the interrupt flag is set, this block signals an interrupt to the interrupt controller. The interrupt controller judges the priority levels of the simultaneous interrupts, and issues an interrupt request to the F MC-16LX CPU if the interrupt from this block has the highest priority.
Page 302 Write address Data bus pin Read data Write data Read signal Write signal Cancel within three machine cycles. Figure 17.3-3 Sample Interface to the External Peripheral Data, address Internal bus CORE MEMORY Cancel within three machine cycles after transfer. MB90390 series...
Page 303: Switching Between External Interrupt And Dtp Requests
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4 Switching between External Interrupt and DTP Requests To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this block, which is in the interrupt controller. Each pin is individually assigned ICR.
Page 304: Notes On Using Dtp/External Interrupts
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.5 Notes on Using DTP/External Interrupts Note carefully the following items when using DTP/external interrupts: • Conditions on the externally connected peripheral when DTP is used • External interrupt/DTP operation procedure • External interrupt request level ■...
Page 305 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Figure 17.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller while Interrupts are Enabled "H" level Interrupt cause Interrupt request to the interrupt controller Set inactive when the cause F/F is cleared.
Page 306 CHAPTER 17 DTP/EXTERNAL INTERRUPTS...
Page 307 CHAPTER 18 8/10-BIT A/D CONVERTER This chapter describes the functions and operation of the 8/10-bit A/D converter. 18.1 Outline of the 8/10-Bit A/D Converter 18.2 Configuration of the 8/10-Bit A/D Converter 18.3 8/10-Bit A/D Converter Pins 18.4 8/10-Bit A/D Converter Registers 18.5 8/10-Bit A/D Converter Interrupts 18.6 Operation of the 8/10-Bit A/D Converter 18.7 Notes on the 8/10-Bit A/D Converter...
Page 308: Chapter 18 8/10-Bit A/D Converter
• The conversion can be activated by software, 16-bit reload timer 1 (rising edge), and external trigger ADTG. • The MB90390 series has 15 analog inputs, where from either channels 0 to 7 or channels 8 to 14 can be selected as inputs for the A/D converter.
Page 309 CHAPTER 18 8/10-BIT A/D CONVERTER Table 18.1-2 8/10-bit A/D Converter Interrupts and EI Interrupt control register Vector table address Interrupt No. Register Address Lower Upper Bank name ❍ #31 (1F ICR10 0000BA FFFF80 FFFF81 FFFF82 ❍ : Available...
Page 310: Configuration Of The 8/10-Bit A/D Converter
CHAPTER 18 8/10-BIT A/D CONVERTER 18.2 Configuration of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has nine blocks: • A/D control status register (ADCS0, ADCS1) • A/D data register (ADCR0, ADCR1) • Clock selector (Input clock selector for activating A/D conversion) •...
Page 311 CHAPTER 18 8/10-BIT A/D CONVERTER ● A/D control status register (ADCS0, ADCS1) This register selects activation by software or another activation trigger, the conversion mode, and the A/D conversion channel. It also enables or disables interrupt requests, checks the interrupt request status, and indicates whether the conversion has halted or is in progress.
Page 312: 8/10-Bit A/D Converter Pins
CHAPTER 18 8/10-BIT A/D CONVERTER 18.3 8/10-Bit A/D Converter Pins This section describes the 8/10-bit A/D converter pins and provides pin block diagrams. ■ 8/10-bit A/D Converter Pins The A/D converter pins are also used as general ports. Table 18.3-1 8/10-bit A/D Converter Pins Pull-up Standby Function...
Page 313 CHAPTER 18 8/10-BIT A/D CONVERTER ■ Analog Input Enable Registers Figure 18.3-1 shows the analog input enable registers (ADER1/ADER0). Figure 18.3-1 Analog Input Enable Registers (ADER1/ADER0) Address: 00000D ADER1/ADER0 ADSEL ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 00000C R/W R/W R/W R/W...
Page 314: 8/10-Bit A/D Converter Registers
CHAPTER 18 8/10-BIT A/D CONVERTER 18.4 8/10-Bit A/D Converter Registers This section lists the 8/10-bit A/D converter registers. ■ 8/10-bit A/D Converter Registers Figure 18.4-1 8/10-bit A/D Converter Registers Address: 11 10 00000D / 00000C ADER1 ADER0 000035 / 000034 ADCS1 ADCS0 000037...
Page 315: Analog Input Enable / A/D Converter Select Register
18.4.1 Analog Input Enable / A/D Converter Select Register The MB90390 series has 15 analog inputs but only one A/D converter with 8 inputs. Therefore, the special bit ADSEL can be used to select the analog input channels. ■ Upper Bits of the Analog Input Enable / A/D Converter Select Register (ADER1) Figure 18.4-2 Configuration of the Upper Bits of Analog Input Enable / A/D Converter Select Register...
Page 316: A/D Control Status Register 1 (Adcs1)
CHAPTER 18 8/10-BIT A/D CONVERTER 18.4.2 A/D Control Status Register 1 (ADCS1) A/D control status register 1 (ADCS1) selects activation by software or activation trigger, enables or disables interrupt requests, and indicates interrupt request status and whether conversion is halted or in progress. ■...
Page 317 CHAPTER 18 8/10-BIT A/D CONVERTER Table 18.4-1 Function Description of Each Bit of Control Status Register 1 (ADCS1) Bit name Function • This bit indicates the operating status of the A/D converter. • If the value read from this bit is "0", A/D conversion has halted. If the read value is "1", A/D conversion is in progress.
Page 318: A/D Control Status Register 0 (Adcs0)
CHAPTER 18 8/10-BIT A/D CONVERTER 18.4.3 A/D control status register 0 (ADCS0) A/D control status register 0 (ADCS0) selects the conversion mode and A/D conversion channel. ■ A/D Control Status Register 0 (ADCS0) Figure 18.4-5 Configuration of the A/D Control Status Register 0 (ADCS0) bit6 bit5 bit4...
Page 319 CHAPTER 18 8/10-BIT A/D CONVERTER Table 18.4-2 Function Description of Each Bit of Control Status Register 0 (ADCS0) Bit name Function • These bits select the conversion mode of the A/D conversion function. • The two-bit value of the MD1 and MD0 bits determines the mode that is selected from among four modes: single conversion mode 1, single conversion mode 2, continuous conversion mode, and stop conversion mode.
Page 320: A/D Data Register (Adcr0, Adcr1)
CHAPTER 18 8/10-BIT A/D CONVERTER 18.4.4 A/D Data Register (ADCR0, ADCR1) The A/D data register (ADCR0, ADCR1) holds the result of A/D conversion and selects the resolution of A/D conversion. ■ A/D Data Register (ADCR0, ADCR1) Figure 18.4-6 A/D Data Register (ADCR0, ADCR1) bit15 bit14 bit13 bit12 bit11 bit10...
Page 321 CHAPTER 18 8/10-BIT A/D CONVERTER Table 18.4-3 Function Description of Each Bit of A/D Data Register 0 (ADCR0) Bit name Function • This bit selects an A/D conversion resolution. S10: • Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a A/D conversion bit15 resolution of 8 bits.
Page 322: 8/10-Bit A/D Converter Interrupts
CHAPTER 18 8/10-BIT A/D CONVERTER 18.5 8/10-Bit A/D Converter Interrupts The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D conversion is set in the A/D data register. This function supports the extended intelligent I/O service (EI OS).
Page 323: Operation Of The 8/10-Bit A/D Converter
CHAPTER 18 8/10-BIT A/D CONVERTER 18.6 Operation of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has three conversion modes: single conversion mode, continuous conversion mode, and stop conversion mode. This section describes operation in each mode. ■ Operation in Single Conversion Mode In single conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted.
Page 324 CHAPTER 18 8/10-BIT A/D CONVERTER ■ Operation in Stop Conversion Mode In stop conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted with a pause after the conversion of each channel. When the end channel specified by the ANE bits has been processed, A/D conversion, with pauses, starts again with the channel specified by the ANS bits.
Page 325: Conversion Using Ei 2 Os
CHAPTER 18 8/10-BIT A/D CONVERTER 18.6.1 Conversion using EI The 8/10-bit A/D converter can use EI OS transfer the A/D conversion result to memory. ■ Conversion Using EI Figure 18.6-3 shows the sample operation flowchart when EI OS is used. Figure 18.6-3 Sample Operation Flowchart when EI OS is Used.
Page 326: A/D Conversion Data Protection Function
CHAPTER 18 8/10-BIT A/D CONVERTER 18.6.2 A/D conversion data protection function When A/D conversion is performed in the interrupt enabled state, the conversion data protection function operates. ■ A/D Conversion Data Protection Function The A/D converter has just one data register that holds conversion data. When a single A/D conversion is completed, the data in the data register is rewritten.
Page 327 CHAPTER 18 8/10-BIT A/D CONVERTER Figure 18.6-4 Operation Flowchart of the Data Protection Function when EI OS is Used Set EI Start continuous A/D conversion End first conversion Store data in the data register Activate EI End second conversion Has EI Halt A/D ended? Store data in the data...
Page 328: Notes On The 8/10-Bit A/D Converter
CHAPTER 18 8/10-BIT A/D CONVERTER 18.7 Notes on the 8/10-Bit A/D Converter Notes on using the 8/10-bit A/D converter. ■ Usage Notes on the 8/10-bit A/D Converter ● Analog input pin The A/D input pins are also used as the I/O pins of ports 6 and B. The corresponding Data Direction Register (DDR6 and DDRB) and the Analog Input Enable Register (ADER) determine which pin is used for which purpose.
Page 329: Sample Program 1 For The 8/10-Bit A/D Converter (Single Conversion Mode Using Ei 2 Os)
CHAPTER 18 8/10-BIT A/D CONVERTER 18.8 Sample Program 1 for the 8/10-Bit A/D Converter (Single Conversion Mode Using EI This section contains a sample program for A/D conversion in single conversion mode using EI ■ Sample Program for Single Conversion Mode Using EI ●...
Page 330 CHAPTER 18 8/10-BIT A/D CONVERTER ● Coding example BAPL 000100H ;Lower buffer address pointer BAPM 000101H ;Intermediate buffer address pointer BAPH 000102H ;Upper buffer address pointer ISCS 000103H OS status register IOAL 000104H ;Lower I/O address register IOAH 000105H ;Upper I/O address register DCTL 000106H ;Lower data counter...
Page 331 CHAPTER 18 8/10-BIT A/D CONVERTER ;-----Interrupt program---------------------------------------------------------- ED_INT1: I:ADCS1,#00H ;Stops A/D conversion. Clears and disables the ;interrupt flag. RETI ;Returns from interrupt. CODE ENDS ;-----Vector setting------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFB4H ;Sets vector for interrupt #18 (12H) ED_INT1 0FFDCH ; Sets reset vector. START ;...
Page 332: Sample Program 2 For The 8/10-Bit A/D Converter (Continuous Conversion Mode Using Ei 2 Os)
CHAPTER 18 8/10-BIT A/D CONVERTER 18.9 Sample Program 2 for the 8/10-Bit A/D Converter (Continuous Conversion Mode Using EI This section contains a sample program for A/D conversion in continuous conversion mode using EI ■ Sample Program for Continuous Conversion Mode Using EI ●...
Page 333 CHAPTER 18 8/10-BIT A/D CONVERTER ● Coding example BAPL 000100H ;Lower buffer address pointer BAPM 000101H ;Middle buffer address pointer BAPH 000102H ;Upper buffer address pointer ISCS 000103H OS status register IOAL 000104H ;Lower I/O address register IOAH 000105H ;Upper I/O address register DCTL 000106H ;Lower data counter...
Page 334 CHAPTER 18 8/10-BIT A/D CONVERTER LOOP: A,#00H ;Endless loop A,#01H LOOP ;-----Interrupt program---------------------------------------------------------- ED_INT1: I:ADCS1,#80H ;Does not stop A/D conversion. Clears and disables ;the interrupt flag. RETI ;Returns from interrupt. CODE ENDS ;-----Vector setting------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFB4H ;Sets vector for interrupt #18 (12 ED_INT1 0FFDCH ;Sets reset vector.
Page 335: Sample Program 3 For The 8/10-Bit A/D Converter (Stop Conversion Mode Using Ei Os)
CHAPTER 18 8/10-BIT A/D CONVERTER 18.10 Sample Program 3 for the 8/10-Bit A/D Converter (Stop Conversion Mode Using EI This section contains a sample program for A/D conversion in stop conversion mode using EI ■ Sample Program for Stop Conversion Mode Using EI ●...
Page 336 CHAPTER 18 8/10-BIT A/D CONVERTER ● Coding example BAPL 000100H ;Lower buffer address pointer BAPM 000101H ;Middle buffer address pointer BAPH 000102H ;Upper buffer address pointer ISCS 000103H OS status register IOAL 000104H ;Lower I/O address register IOAH 000105H ;Upper I/O address register DCTL 000106H ;Lower data counter...
Page 337 CHAPTER 18 8/10-BIT A/D CONVERTER ;-----Interrupt program---------------------------------------------------------- ED_INT1: I:ADCS1,#80H ;Does not stop A/D conversion. Clears and disables ;the interrupt flag. RETI ;Returns from interrupt. CODE ENDS ;-----Vector setting------------------------------------------------------------- VECT CSEG ABS=0FFH 0FFB4H ;Sets vector for interrupt #18 (12 ED_INT1 0FFDCH ;Sets reset vector.
Page 338 CHAPTER 18 8/10-BIT A/D CONVERTER...
Page 339: Chapter 19 Uart0, Uart1
UART0, UART1 This chapter explains the UART0, UART1 functions and operations. Note: UART2 is not specified in the MB90390 series. For this reason Fujitsu recommends not to use this feature. 19.1 Features of UART0, UART1 19.2 UART0, UART1 Block Diagram 19.3 UART0, UART1 Registers...
Page 340: Features Of Uart0, Uart1
19.1 Features of UART0, UART1 The UART0, UART1 are serial I/O ports for asynchronous or CLK synchronous communication. The MB90390 Series contains four UARTs. For UART2 and UART3 see "CHAPTER 20 UART2, UART3". ■ Feature of UART0, UART1 UART0, UART1 have the following features each.
Page 341: Uart0, Uart1 Block Diagram
CHAPTER 19 UART0, UART1 19.2 UART0, UART1 Block Diagram Figure 19.2-1 shows the UART0, UART1 block diagram. ■ UART0, UART1 Block Diagram Figure 19.2-1 UART0, UART1 Block Diagram CONTROL BUS Receive interrupt (to CPU) Dedicated baud rate clock SCK0 T r ansmit clock T r ansmit interrupt 16-bit reload timer 0 (to CPU)
Page 342: Uart0, Uart1 Registers
CHAPTER 19 UART0, UART1 19.3 UART0, UART1 Registers The UART0, UART1 have the following four registers each: • Serial mode control register • Status register • Input data register/output data register • Rate and data register ■ UART0, UART1 Registers Serial mode control register Address: ch.0 000020 UMC0...
Page 343: Serial Mode Control Register (Umc)
CHAPTER 19 UART0, UART1 19.3.1 Serial Mode Control Register (UMC) UMC specifies the operation mode of UART0, UART1. Set the operation mode while operation is halted. However, the RFC bit can be accessed during operation. ■ Serial Mode Control Register (UMC) Figure 19.3-1 Configuration of the Serial Mode Control Register (UMC) UMC0 UMC1 Address:...
Page 344 CHAPTER 19 UART0, UART1 ■ Serial Mode Control Register (UMC) Contents Table 19.3-1 Function of Each Bit of the Serial Control Register Bit name Function Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set to "0" PEN: in mode 2.
Page 345: Status Register (Usr)
CHAPTER 19 UART0, UART1 19.3.2 Status Register (USR) USR indicates the current state of the UART0, UART1 port. ■ Status Register (USR) Figure 19.3-2 Configuration of the Status Register (USR) Address: USR0 USR1 ch.0 000021 Initial value RDRF ORFE TDRE ch.1 000025 0 0 0 1 0 0 0 0 bit8...
Page 346 CHAPTER 19 UART0, UART1 ■ Status Register (USR) Contents Table 19.3-2 Function of Each Bit of the Status Register Bit name Function This flag indicates the state of the UIDR (input data register). The flag is set when the receive data is RDRF: loaded into UIDR.
Page 347: Input Data Register (Uidr) And Output Data Register (Uodr)
CHAPTER 19 UART0, UART1 19.3.3 Input Data Register (UIDR) and Output Data Register (UODR) UIDR (input data register) is the serial data input register. UODR (output data register) is the serial data output register. The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the most significant bit (D7) is ignored if the data length is 7 bits.
Page 348: Rate And Data Register (Urd)
CHAPTER 19 UART0, UART1 19.3.4 Rate and Data Register (URD) URD selects the data transfer speed (baud rate) for UART0, UART1. The register also holds the most significant bit (bit8) of the data when the transmit data length is 9 bits. Set the baud rate and parity when UART0, UART1 is halted.
Page 349 CHAPTER 19 UART0, UART1 ■ Rate and Data Register (URD) Contents Table 19.3-3 Function of Each Bit of the Rate and Data Register Bit name Function Specifies the machine cycles for the baud rate clock (see Section "19.4 UART0, UART1 Operation" for details). Divider BCH0 Setting example for different Machine Cycles...
Page 350: Uart0, Uart1 Operation
CHAPTER 19 UART0, UART1 19.4 UART0, UART1 Operation Table 19.4-1 lists the operating modes for UART0, UART1. Set the UMC register to switch between modes. ■ UART0, UART1 Operation Modes Table 19.4-1 UART0, UART1 Operating Modes Mode Parity Data Length Clock Mode Length of Stop Bits CLK asynchronous or...
Page 351: Baud Rate
CHAPTER 19 UART0, UART1 19.5 Baud Rate When the dedicated baud rate generator is used, the following two types of baud rates are available: • CLK synchronous baud rate • CLK asynchronous baud rate ■ CLK Synchronous Baud Rate The five URD register bits: BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLK synchronous transfer.
Page 352 CHAPTER 19 UART0, UART1 ■ CLK Asynchronous Baud Rate The six URD register bits: BCH, BCH0 and RC3, RC2, RC1, RC0 select the baud rate for CLK asynchronous transfer. First select the machine clock divider ratio using BCH and BCH0. BCH BCH0 -->...
Page 353 CHAPTER 19 UART0, UART1 Table 19.5-1 Baud Rate CLK asynchronous (μs/bps) CLK synchronous (μs/bps) 24 MHz 20 MHz 16 MHz 12 MHz 24 MHz 20 MHz 16 MHz 12 MHz asynchronous divider ratio BCH/ BCH/ BCH/ BCH/ BCH/ BCH/ BCH/ BCH/ BCH0= BCH0=...
Page 354: Internal And External Clock
CHAPTER 19 UART0, UART1 19.6 Internal and External Clock Setting RC3 to RC0 to "1101 " selects the clock signal from the 16-bit Reload Timer. Setting RC3 to RC0 to "1111 " selects the external clock. The external clock frequency has a maximum value of 2 MHz. ■...
Page 355: Transfer Data Format
CHAPTER 19 UART0, UART1 19.7 Transfer Data Format UART0, UART1 only handle NRZ (non-return-to-zero) type data. Figure 19.7-1 shows the relationship between the transmit/receive clock and the data for CLK synchronous mode. ■ Transfer Data Format Figure 19.7-1 Transfer Data Format SCK0 SIN0, SOT0 ⎫...
Page 356: Parity Bit
CHAPTER 19 UART0, UART1 19.8 Parity Bit The P bit in the URD0, URD1 register specifies whether to use even or odd parity when parity is enabled. The PEN bit in the UMC0, UMC1 register enables parity. ■ Parity Bit Inputting the data shown in Figure 19.8-1 to SIN when even parity is set causes a receive parity error.
Page 357: Interrupt Generation And Flag Set Timings
CHAPTER 19 UART0, UART1 19.9 Interrupt Generation and Flag Set Timings UART0, UART1 have two interrupt causes and six flags each. The two interrupt causes are the receive and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF.
Page 358: Flag Set Timings For A Receive Operation (Mode0, Mode1, Mode3)
CHAPTER 19 UART0, UART1 19.9.1 Flag Set Timings for a Receive Operation (Mode0, Mode1, Mode3) The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated when the final stop bit is detected indicating the end of reception transfer. The data in UIDR0, UIDR1 is invalid when either the ORFE or PE bit is active.
Page 359: Flag Set Timings For A Receive Operation (In Mode 2)
CHAPTER 19 UART0, UART1 19.9.2 Flag Set Timings for a Receive Operation (in Mode 2) The RDRF flag is set when the final stop bit is detected and reception transfer ends with the last data bit (D8) having the value "1". The ORFE flag is set when the final stop bit is detected, irrespective of the value of the last data bit (D8).
Page 360: Flag Set Timings For A Transmit Operation
CHAPTER 19 UART0, UART1 19.9.3 Flag Set Timings for a Transmit Operation TDRE is set and an interrupt request to the CPU is generated when the data written in UODR register is transferred to the internal shift register and the next data can be written to UODR.
Page 361: Status Flag During Transmit And Receive Operation
CHAPTER 19 UART0, UART1 19.9.4 Status Flag During Transmit and Receive Operation RBF is set when the start bit is detected and cleared when a stop bit is detected. The receive data in UIDR at the RBF clear timing is not yet valid. The data in UIDR becomes valid at the RDRF set timing.
Page 362: 19.10 Uart0, Uart1 Application Example
CHAPTER 19 UART0, UART1 19.10 UART0, UART1 Application Example Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure 19.10-1.) ■ Application Example Figure 19.10-1 RBF Set Timing (Mode 0) SIN0 input ST D0 D1 D2 D3 D4 D5 D6 D7...
Page 363 CHAPTER 19 UART0, UART1 Figure 19.10-3 Communication Flowchart for Mode 2 Operation (Host CPU) (Slave CPU) Start Start Set the transfer mode to "3" Set the transfer mode to "2" Receive a byte Set the slave CPU selection in D0 to D7. Set D8 to "1". Transfer the byte.
Page 364 CHAPTER 19 UART0, UART1...
Page 365: Chapter 20 Uart2, Uart3
CHAPTER 20 UART2, UART3 This chapter explains the functions and operation of UART2, UART3. Note: UART2 is only available on MB90V390HA/ MB90V390HB. 20.1 Overview of UART2, UART3 20.2 Configuration of UART2, UART3 20.3 UART2, UART3 Pins 20.4 UART2, UART3 Registers 20.5 UART2, UART3 Interrupts 20.6 UART2, UART3 Baud Rates 20.7 Operation of UART2, UART3...
Page 366: Overview Of Uart2, Uart3
CHAPTER 20 UART2, UART3 20.1 Overview of UART2, UART3 The UART2, UART3 with LIN (Local Interconnect Network) - Function is a general- purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. UART2, UART3 provides bidirectional communication function (normal mode), master/slave communication function (multiprocessor mode in master/slave systems), and special features for LIN- bus systems (working both as master or as slave device).
Page 367 CHAPTER 20 UART2, UART3 Table 20.1-1 UART2, UART3 Functions (2/2) Item Function Master/slave communication function One-to-n communication (one master to n slaves) (multiprocessor mode) (This function is supported both for master and slave system). Synchronous mode Function as Master- or Slave-UART Transceiving pins Direct access possible •...
Page 368 CHAPTER 20 UART2, UART3 ■ UART2, UART3 Operation Modes The UART2, UART3 operates in four different modes, which are determined by the MD0- and the MD1- bit of the Serial mode register (SMR2/SMR3). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication.
Page 369 CHAPTER 20 UART2, UART3 ■ UART2, UART3 Interrupt and EI Table 20.1-4 UART2, UART3 Interrupt and EI Interrupt control register Vector table address Interrupt Interrupt cause number Register Address Lower Upper Bank name UART2 reception interrupt #39(27 0000BE FFFF60 FFFF61 FFFF62 ICR14 UART2 transmission...
Page 370: Configuration Of Uart2, Uart3
CHAPTER 20 UART2, UART3 20.2 Configuration of UART2, UART3 This section provides a short overview on the building blocks of UART2, UART3. ■ Block Diagram of UART2, UART3 UART2, UART3 consists of the following blocks: • Reload Counter • Reception Control Circuit •...
Page 371 CHAPTER 20 UART2, UART3 Figure 20.2-1 Block Diagram of UART2, UART3 (OTO, EXT, Machine clock REST) transmission clock LBIE Reload Interrupt reception clock Counter Generation TRANSMISSION SCK2/SCK3 circuit CONTROL RECEPTION CONTROL CIRCUIT CIRCUIT Start bit Transmission Detection Start circuit reception circuit Restart Reception Reload Counter...
Page 372 CHAPTER 20 UART2, UART3 ■ Explanation of the Different Blocks ● Reload Counter The reload counter functions as the dedicated baud rate generator. It can select external input clock or internal clock for the transmitting and receiving clocks. The reload counter has a 15 bit register for the reload value.
Page 373 CHAPTER 20 UART2, UART3 ● Oversampling Unit The oversampling unit oversamples the incoming data at the SIN2/SIN3 pin for five times with the machine clock. It is not operated in synchronous operation mode. ● Interrupt Generation Circuit The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately.
Page 374 CHAPTER 20 UART2, UART3 ● Serial Status Register (SSR2/SSR3) This register performs the following functions • Indicating status of receive/transmit operations and errors • Specifying LSB first or MSB first • Receive interrupt enable/disable • Transmit interrupt enable/disable ● Extended Status/Control Register (ESCR2/ESCR3) This register performs the following functions •...
Page 375: Uart2, Uart3 Pins
CHAPTER 20 UART2, UART3 20.3 UART2, UART3 Pins This section describes the UART2, UART3 pins and provides a pin block diagram. ■ UART2, UART3 Pins The UART2, UART3 pins also serve as general ports. Table 20.3-1 lists the UART2, UART3 pins. Table 20.3-1 UART2, UART3 Pins Standby Pin name...
Page 376 CHAPTER 20 UART2, UART3 Figure 20.3-1 Block Diagram of UART2, UART3 Pins Resource input * Resource output Port data register (PDR) Resource output enable PDR read P-ch Output latch PDR write Port direction register (DDR) general purpose I/O /SIN2/SIN3 N-ch Direction latch general purpose I/O /SCK2/SCK3 general purpose I/O /SOT2/SOT3...
Page 377: Uart2, Uart3 Registers
CHAPTER 20 UART2, UART3 20.4 UART2, UART3 Registers The following figure shows the UART2, UART3 registers. ■ UART2, UART3 Registers Figure 20.4-1 UART2, UART3 Registers bit 15 bit 8 bit 7 bit 0 Address: SCR3 (Serial Control Register) SMR3 (Serial Mode Register) 003519 , 003518 SSR3 (Serial Status Register)
Page 378: Serial Control Register (Scr2/Scr3)
CHAPTER 20 UART2, UART3 20.4.1 Serial Control Register (SCR2/SCR3) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. ■...
Page 379 CHAPTER 20 UART2, UART3 Table 20.4-1 Functions of Each Bit of Control Register (SCR2/SCR3) Bit name Function This bit selects whether to add a parity bit during transmission or detect it during PEN: reception. bit15 Parity enable bit Parity is only provided in mode 0 and in mode 2 if SSM of the ECCR2/ECCR3 is selected.
Page 380: Serial Mode Register (Smr2/Smr3)
CHAPTER 20 UART2, UART3 20.4.2 Serial Mode Register (SMR2/SMR3) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. ■ Serial Mode Register (SMR2/SMR3) Figure 20.4-3 Configuration of the Serial Mode Register (SMR2/SMR3) Initial value Address: 0 0 0 0 0 0 0 0...
Page 381 CHAPTER 20 UART2, UART3 Table 20.4-2 Bit Function of the Serial Mode Register (SMR2/SMR3) Bit name Function MD1 and MD0: bit7 Operation mode These two bits set the UART2, UART3 operation mode. bit6 selection bits OTO: This bit sets an external clock directly to the LIN-UART2, LIN-UART3’s serial clock. bit5 One-to-one external This function is used for operating mode 2 (synchronous) slave mode operation.
Page 382: Serial Status Register (Ssr2/Ssr3)
CHAPTER 20 UART2, UART3 20.4.3 Serial Status Register (SSR2/SSR3) This register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. ■ Serial Status Register (SSR2/SSR3) Figure 20.4-4 Configuration of the Serial Status Register (SSR2/SSR3) Initial value Address: 0 0 0 0 1 0 0 0...
Page 383 CHAPTER 20 UART2, UART3 Table 20.4-3 Functions of Each Bit of Status Register (SSR2/SSR3) (1/2) Bit name Function • This bit is set to "1" when a parity error occurs during reception at PEN=1 and is cleared when "1" is written to the CRE bit of the serial mode register (SMR2/SMR3). MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected bit15 Parity error flag...
Page 384 CHAPTER 20 UART2, UART3 Table 20.4-3 Functions of Each Bit of Status Register (SSR2/SSR3) (2/2) Bit name Function RIE: • This bit enables/disables the reception interrupt. If any of the RDRF, PE, ORE and FRE Reception bit9 bits is set and this bit is "1", then a reception interrupt is signaled to the interrupt interrupt request controller.
Page 385: Reception And Transmission Data Register (Rdr2/Rdr3 And Tdr2/Tdr3)
CHAPTER 20 UART2, UART3 20.4.4 Reception and Transmission Data Register (RDR2/RDR3 and TDR2/TDR3) The reception data register (RDR2/RDR3) holds the received data. The transmission data register (TDR2/TDR3) holds the transmission data. Both RDR2/RDR3 and TDR2/ TDR3 registers are located at the same address. ■...
Page 386 CHAPTER 20 UART2, UART3 ■ Transmission Data Register (TDR2/TDR3) When data to be transmitted is written to the transmission data register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output terminal (SOT2/SOT3 pin).
Page 387: Extended Status/Control Register (Escr2/Escr3)
CHAPTER 20 UART2, UART3 20.4.5 Extended Status/Control Register (ESCR2/ESCR3) The extended status control register (ESCR2/ESCR3) provides several functions, such as LIN synch break interrupt enabling/disabling, LIN synch break length selection, LIN synch break detection, direct access to the SIN2/SIN3 and SOT2/SOT3 pins, continuous clock output in UART2, UART3 synchronous clock mode, and sampling clock edge setting.
Page 388 CHAPTER 20 UART2, UART3 Table 20.4-4 Function of Each Bit of the Extended Status/Control Register (ESCR2/ESCR3) Bit name Function LBIE: This bit enables/disables LIN synch break interrupt. LIN synch break LIN synch break interrupt is connected to the reception interrupt. When the LBD bit is bit15 detection interrupt set and this bit is "1", a reception interrupt is signaled to the interrupt controller.
Page 389 CHAPTER 20 UART2, UART3 Table 20.4-5 Description of the Interaction of SOPE and SIOP SOPE SIOP Writing to SIOP Reading from SIOP write "0" or "1" to SOT2/SOT3 returns current value of SIN2/SIN3 reads current value of SOT2/SOT3 and write "0" or "1" - : "0"...
Page 390: Extended Communication Control Register (Eccr2/Eccr3)
CHAPTER 20 UART2, UART3 20.4.6 Extended Communication Control Register (ECCR2/ ECCR3) The extended communication control register provides bus idle recognition interrupt settings, synchronous clock settings, and the LIN Synch break generation. ■ Extended Communication Control Register (ECCR2/ECCR3) Figure 20.4-7 shows the bit configuration of the extended communication control registers (ECCR2/ ECCR3), and Table 20.4-6 shows the functions of each bit in the resisters.
Page 391 CHAPTER 20 UART2, UART3 Table 20.4-6 Function of Each Bit of the Extended Communication Control Register (ECCR2/ECCR3) Bit name Function bit7 This bit is undefined. Always write "0". Writing a "1" to this bit generates a LIN synch break of the length selected by the LBL0/ LBR: Generating bit6 LBL1 bits of the ESCR2/ESCR3, if operation mode 3 is selected.
Page 392: Baud Rate Generator Register 0 And 1 (Bgr02/03 And Bgr12/13)
CHAPTER 20 UART2, UART3 20.4.7 Baud Rate Generator Register 0 and 1 (BGR02/03 and BGR12/13) The baud rate generator registers 0 and 1 (BGR02/03 and BGR12/13) set the division ratio for the serial clock. Also the actual count of the transmission reload counter can be read.
Page 393: Uart2, Uart3 Interrupts
CHAPTER 20 UART2, UART3 20.5 UART2, UART3 Interrupts UART2, UART3 uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the Reception Data Register (RDR2/RDR3), or a reception error occurs.
Page 394 CHAPTER 20 UART2, UART3 ● Reception Interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status Register (SSR2/SSR3) is set to "1": • Data reception is complete, i. e. the received data was transferred from the received shift register to the Reception Data Register (RDR2/RDR3): (RDRF=1) •...
Page 395 CHAPTER 20 UART2, UART3 MB90V390HA/MB90V390HB/MB90394HA: This paragraph is only relevant, if UART2, 3 operates in mode 3 as a LIN slave. If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag bit of the Extended Status/Control Register (ESCR2/ESCR3) is set to "1".
Page 396 CHAPTER 20 UART2, UART3 ■ UART2, UART3 EI OS Functions UART2, UART3 has a circuit for operating EI OS, which can be started up for either reception or transmission interrupts. ● For UART2 Reception UART2 shares the interrupt registers with the UART2 transmission interrupts and with UART3 reception and transmission interrupts.
Page 397: Reception Interrupt Generation And Flag Set Timing
CHAPTER 20 UART2, UART3 20.5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: completion of reception (SSR2/SSR3: RDRF) and occurrence of a reception error (SSR2/SSR3:PE, ORE, or FRE). ■ Reception Interrupt Generation and Flag Set Timing The first stop bit detection in mode 0, 1, 2 (SSM = 1), 3, or the last data bit detection in mode 2 (SSM = 0) will store the reception data into the reception data resisters (RDR2/RDR3).
Page 398 CHAPTER 20 UART2, UART3 Figure 20.5-2 ORE Set Timing Receive data RDRF...
Page 399: Transmission Interrupt Generation And Flag Set Timing
CHAPTER 20 UART2, UART3 20.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDR2/TDR3) to transmission shift register and started. ■ Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated, when the next data to be sent is ready to be written to the Transmission Data Register (TDR2/TDR3), i.
Page 400 CHAPTER 20 UART2, UART3 ■ Transmission Interrupt Request Generation Timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR2/SSR3: TIE=1), transmission interrupt request is generated. Note: A transmission completion interrupt is generated immediately after the transmission interrupt is enabled (TIE=1) because the TDRE bit is set to "1"...
Page 401: Uart2, Uart3 Baud Rates
CHAPTER 20 UART2, UART3 20.6 UART2, UART3 Baud Rates One of the following can be selected for the UART2, UART3 serial clock source: • Dedicated baud rate generator (Reload Counter) • External clock as it is (clock input to the SCK2/SCK3 pin) •...
Page 402 CHAPTER 20 UART2, UART3 Figure 20.6-1 Baud Rate Selection Circuit (Reload Counter) REST Start bit falling Reload Value: v edge detected Rxc = 0? Reception Reception Reload Clock 15-bit Reload Counter reset Rxc = v/2? Reload Value: v Machine clock Txc = 0? Transmission 15-bit Reload Counter...
Page 403: Setting The Baud Rate
CHAPTER 20 UART2, UART3 20.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the Baud Rate Both 15-bit reload counters are programmed by the baud rate generator registers 0, 1 (BGR02/03 and BGR12/13).
Page 404 CHAPTER 20 UART2, UART3 ■ Suggested Division Ratios for Different Machine Speeds and Baud Rates The following settings are suggested for different MCU clock speeds and baud rates: Table 20.6-1 Suggested Baud Rates and Reload Values at Different Machine Speeds Baud 8 MHz 10 MHz...
Page 405 CHAPTER 20 UART2, UART3 ■ Using External Clock If the EXT bit of the SMR2/SMR3 is set, an external clock is selected, which has to be connected to the SCK2/SCK3 pin. The external clock is used in the same way as the machine clock to the baud rate reload counter.
Page 406: Reload Counter
CHAPTER 20 UART2, UART3 20.6.2 Reload Counter This is the 15-bit reload counter that works as a dedicated baud rate generator, and generates the transmission/reception clock through the external or internal clock. In addition, it can read the value of the transmission reload counter from the baud rate generator registers (BGR02/BGR03, BGR12/BGR13).
Page 407 CHAPTER 20 UART2, UART3 Figure 20.6-3 Reload Counter Restart Example Clock Reload Counter Clock Outputs REST Reload Value Read BGR02/03, BGR12/BGR13 Data : don’t care In this example the number of MCU clock cycles (cyc) after REST is then: cyc = v - c + 1 = 100 - 90 + 1 = 11 where v is the reload value and c is the read counter value.
Page 408: Operation Of Uart2, Uart3
CHAPTER 20 UART2, UART3 20.7 Operation of UART2, UART3 UART2, UART3 operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication. ■...
Page 409 CHAPTER 20 UART2, UART3 ■ Inter-CPU Connection Method External Clock One-to-one connection (normal mode) and master/slave connection (multiprocessor mode) can be selected. For either connection method, the data length, whether to enable parity, and the synchronization method must be common to all CPUs. Select an operation mode as follows: •...
Page 410: Operation In Asynchronous Mode (Op. Modes 0 And 1)
CHAPTER 20 UART2, UART3 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) When UART2, UART3 is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■ Operation in Asynchronous Mode ●...
Page 411 CHAPTER 20 UART2, UART3 ● Transmission operation If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR2/SSR3) is "1", transmission data is allowed to be written to the Transmission Data Register (TDR2/TDR3). When data is written, the TDRE flag goes "0".
Page 412 CHAPTER 20 UART2, UART3 ● Error detection In mode 0, parity, overrun, and frame errors can be detected. In mode 1, overrun and frame errors can be detected; parity errors cannot be detected though. ● Parity The addition and detection of a parity bit can be set (for transmission and reception, respectively). Use the parity enable bit (SCR2/SCR3:PEN) to enable or disable parity and the parity selection bit (SCR2/SCR3:P) to select even or odd parity.
Page 413: Operation In Synchronous Mode (Operation Mode 2)
CHAPTER 20 UART2, UART3 20.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for UART2, 3 operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation Mode 2) ● Transfer data format In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR2/ECCR3) is "0".
Page 414 CHAPTER 20 UART2, UART3 ● Clock supply In clock synchronous mode (normal), the number of clock cycles for the clock signal must be the same as the number of transmission and reception bits for the data including start and stop bits. If the MS bit of the ECCR2/ECCR3 register is "0"...
Page 415 CHAPTER 20 UART2, UART3 ● Error detection If no start/stop bits are selected (ECCR2/ECCR3: SSM = 0) only overrun errors are detected. ● Communication For initialization of the synchronous mode, following settings have to be done: Baud rate generator registers (BGR02/BGR03 and BGR12/BGR13): Set the desired reload value for the dedicated baud rate reload counter.
Page 416: Operation With Lin Function (Operation Mode 3)
CHAPTER 20 UART2, UART3 20.7.3 Operation with LIN Function (Operation Mode 3) UART2, UART3 can be used either as LIN-Master or LIN-Slave. For this LIN function a special mode is provided. Setting the UART2, UART3 to mode 3 configures the data format to 8N1-LSB-first format.
Page 417 CHAPTER 20 UART2, UART3 ● UART2, UART3 as LIN slave In LIN slave mode UART2, UART3 has to synchronize to the master’s baud rate. If Reception is disabled (RXE = 0) but LIN break Interrupt is enabled (LBIE = 1) UART2, UART3 will generate a reception interrupt, if a synchronization break from the LIN master is detected, and indicates it with the LBD flag of the ESCR2/ESCR3.
Page 418 CHAPTER 20 UART2, UART3 ● LIN Synch Break Detection Interrupt and Flags If a LIN Synch synchronization break is detected in the slave mode, the LIN Break Detected (LBD) Flag of the ESCR2/ESCR3 is set to "1". This causes an interrupt, if the LIN Break Interrupt Enable (LBIE) bit is set.
Page 419 CHAPTER 20 UART2, UART3 ● LIN bus timing Figure 20.7-9 LIN Bus Timing and UART2, UART3 Signals no clock used (calibration frame) old serial clock new (calibrated) serial clock ICU count (SIN2/SIN3) (IRQ0) LBIE Internal Signal to ICU IRQ from RDRF (IRQ0) Read...
Page 420: Direct Access To Serial Pins
CHAPTER 20 UART2, UART3 20.7.4 Direct Access to Serial Pins UART2, UART3 allows the user to directly access to the transmission pin (SOT2, SOT3) or the reception pin (SIN2, SIN3). ■ UART2, UART3 Direct Pin Access The UART2, UART3 provides the ability for the software to access directly to serial input or output pin. The states of serial input pins (SIN2/SIN3) can be read via the serial I/O pin direct access bits (ESCR2/ ESCR3:SIOP).
Page 421: Bidirectional Communication Function (Normal Mode)
CHAPTER 20 UART2, UART3 20.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in Figure 20.7-10 are required to operate UART2, UART3 in normal mode (operation mode 0 or 2).
Page 422 CHAPTER 20 UART2, UART3 ● Inter-CPU connection As shown in Figure 20.7-11, interconnect two CPUs in UART2, UART3 mode 2 Figure 20.7-11 Connection Example of UART2, UART3 Mode 2 Bidirectional Communication Input Output CPU-1 (Master) CPU-2 (Slave) ● Communication procedures Communication will start at any timing from the transmission side when the transmission data is ready.
Page 423: Master/Slave Communication Function (Multiprocessor Mode)
CHAPTER 20 UART2, UART3 20.7.6 Master/Slave Communication Function (Multiprocessor Mode) UART2, UART3 communication with multiple CPUs connected in master/slave mode is available for both master or slave systems. ■ Master/Slave Communication Function The settings shown in Figure 20.7-13 are required to operate UART2, UART3 in multiprocessor mode (operation mode 1).
Page 424 CHAPTER 20 UART2, UART3 ● Inter-CPU connection As shown in Figure 20.7-14, a communication system consists of one master CPU and multiple slave CPUs connected to two communication lines. UART2, UART3 can be used for the master or slave CPU. Figure 20.7-14 Connection Example of UART2, UART3 Master/Slave Communication SOT1 SIN1...
Page 425 CHAPTER 20 UART2, UART3 Figure 20.7-15 Master/Slave Communication Flowchart (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SIN2/SIN3 pin as the Set SIN2/SIN3 pin as the serial data input pin. serial data input pin. Set SOT2/SOT3 pin as the Set SOT2/SOT3 pin as the serial data output pin.
Page 426: Lin Communication Function
CHAPTER 20 UART2, UART3 20.7.7 LIN Communication Function UART2, UART3 communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN-master/slave Communication Function The settings shown in the figure below are required to operate UART2, UART3 in LIN communication mode (operation mode 3).
Page 427: Sample Flowcharts For Uart2, Uart3 In Lin Communication (Operation Mode 3)
CHAPTER 20 UART2, UART3 20.7.8 Sample Flowcharts for UART2, UART3 in LIN Communication (Operation Mode 3) This section contains sample flowcharts for UART2, UART3 in LIN communication. ■ UART2, UART3 as Master Device Figure 20.7-18 UART2, UART3 LIN Master Flow Chart START Initial setting : Set operation mode 3...
Page 428 CHAPTER 20 UART2, UART3 ■ UART2, UART3 as Slave Device Figure 20.7-19 UART2, UART3 LIN Slave Flow Chart START Initial setting : Set operation mode 3 Serial data output enabled Baud rate setting Synch break length setting TXE=1, TIE=0 RXE=0, RIE=1 Connection with UART and ICU Reception prohibited ICU interrupt enabled...
Page 429: Notes On Using Uart2, Uart3
CHAPTER 20 UART2, UART3 20.8 Notes on Using UART2, UART3 Notes on using UART2, UART3 are given below. ■ Notes on Using UART2, UART3 ● Enabling operations In UART2, UART3, the serial control register (SCR2/SCR3) has TXE (transmission) and RXE (reception) operation enable bits.
Page 430 CHAPTER 20 UART2, UART3 ● Using LIN operation mode 3 The LIN features are available in mode 3 (transmitting, receiving synch break), but using mode 3 sets the UART2, UART3 data format automatically to LIN format (8N1, LSB first). Note, that the length of the synch break for transmission is variable but for reception it is fixed 11-bit times.
Page 431 CHAPTER 20 UART2, UART3 ● A/D bit (serial control register (SCR2/SCR3): address/data type select bit) The behavior of this bit is different between MB90V390H/MB90F394H(A) and MB90V390HA/ MB90V390HB/MB90394HA. MB90V390H/MB90F394H(A): • Special care has to be taken when using the A/D bit (Address-Data-Bit for multiprocessor mode 1) of the Serial Control Register.
Page 432 CHAPTER 20 UART2, UART3...
Page 433: Chapter 21 400 Khz I 2 C Interface
CHAPTER 21 400 kHz I C INTERFACE This section describes the functions and operation of the fast I C interface. Note: The I C interface is not available in all MB90390 Series devices. 21.1 I C Interface Overview 21.2 I C Interface Registers 21.3 I C Interface Operation...
Page 434: I 2 C Interface Overview
CHAPTER 21 400 kHz I C INTERFACE 21.1 C Interface Overview The I C interface is a serial I/O port supporting the Inter IC bus, operating as a master/ slave device on the I C bus. ■ Features • Master/slave transmitting and receiving functions •...
Page 435 CHAPTER 21 400 kHz I C INTERFACE ■ Block Diagram of I C Interface Figure 21.1-1 shows the block diagram of the I C interface. Figure 21.1-1 Block Diagram of I C Interface ICCR C enable ICCR Clock Divider 1 2 3 4 5 ...
Page 436: I 2 C Interface Registers
CHAPTER 21 400 kHz I C INTERFACE 21.2 C Interface Registers This section describes the function of the I C interface registers in detail. ■ I C Interface Registers Bus Control Register (IBCR) IBCR Address: BER BEIE SCC MSS ACK GCAA INTE 0035A1 Initial value 0 0 0 0 0 0 0 0...
Page 437 CHAPTER 21 400 kHz I C INTERFACE Seven bit slave address MasK register (ISMK) ISMK ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0 0035A7 Initial value 0 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W Data Register (IDAR) IDAR D7 D6 D5 D4 D3 D2 D1 D0...
Page 438: Bus Status Register (Ibsr)
CHAPTER 21 400 kHz I C INTERFACE 21.2.1 Bus Status Register (IBSR) The bus status register (IBSR) has the following functions: • Bus busy detection • Repeated start condition detection • Arbitration loss detection • Acknowledge detection • Data transfer direction indication •...
Page 439 CHAPTER 21 400 kHz I C INTERFACE ■ Bus Status Register (IBSR) Contents Table 21.2-1 Function of Each Bit of the Bus Status Register (IBSR) (1/2) Bit name Function This bit indicates the status of the I C bus. "0": Stop condition detected (bus idle) bit7 Bus busy bit "1": Start condition detected (bus in use)
Page 440 CHAPTER 21 400 kHz I C INTERFACE Table 21.2-1 Function of Each Bit of the Bus Status Register (IBSR) (2/2) Bit name Function This bit indicates detection of a general call address (00 GCA: "0": General call address not received as slave. bit1 General call "1": General call address received as slave.
Page 441: Bus Control Register (Ibcr)
CHAPTER 21 400 kHz I C INTERFACE 21.2.2 Bus Control Register (IBCR) The bus control register (IBCR) has the following functions: • Interrupt enabling flags • Interrupt generation flag • Bus error detection flag • Repeated start condition generation • Master / slave mode selection •...
Page 442 CHAPTER 21 400 kHz I C INTERFACE Figure 21.2-2 Configuration of the Bus Control Register IBCR Address: BER BEIE SCC MSS ACK GCAA INTE 0035A1 Initial value 0 0 0 0 0 0 0 0 R/W R/W W R/W R/W R/W bit 8 Interrupt bit see table on next page for details...
Page 443 CHAPTER 21 400 kHz I C INTERFACE ■ Bus Control Register (IBCR) Contents Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (1/3) Bit name Function This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user. It always reads "1"...
Page 444 CHAPTER 21 400 kHz I C INTERFACE Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (2/3) Bit name Function This is the master/slave mode selection bit. It can only be set by the user, but it can be cleared by the user and the hardware.
Page 445 CHAPTER 21 400 kHz I C INTERFACE Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (3/3) Bit name Function This bit is the transfer end interrupt request flag. It is changed by the hardware and can be cleared by the user.
Page 446 CHAPTER 21 400 kHz I C INTERFACE ■ SCC, MSS and INT Bit Competition Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as follows: •...
Page 447 If the device is used in the following condition, it cannot receive as slave. So, sending general call address is prohibited. - Condition that there is other master mode LSI on the bus without MB90390 series, and MB90390 series transmit the general-call address as master, and the arbitration lost occurs after second byte.
Page 448 CHAPTER 21 400 kHz I C INTERFACE - Condition 2 in which an interrupt (INT bit = 1) upon detection of " AL bit = 1 " does not occurs When an instruction which generates a start condition by enabling I C operation (EN bit = 1) is executed (setting the MSS bit in the IBCR register to "1") with the I C bus occupied by another...
Page 449 CHAPTER 21 400 kHz I C INTERFACE A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR) to "1". Wait * for the time of three-bit data transmission at the I transfer frequency set in the clock control register (ICCR).
Page 450: Ten Bit Slave Address Register (Itba)
CHAPTER 21 400 kHz I C INTERFACE 21.2.3 Ten Bit Slave Address Register (ITBA) This register (ITBAH / ITBAL) designates the ten bit slave address. ■ Ten Bit Slave Address Register (ITBA) Write access to this register is only possible if the interface is disabled (EN= 0 in ICCR). ITBAH (upper) Address: 0035A3...
Page 451: Ten Bit Address Mask Register (Itmk)
CHAPTER 21 400 kHz I C INTERFACE 21.2.4 Ten Bit Address Mask Register (ITMK) This register contains the ten bit slave address mask and the ten bit slave address enable bit. ■ Ten Bit Address Mask Register (ITMK) ITMKH (upper) Address: 0035A5 ENTB RAL...
Page 452 CHAPTER 21 400 kHz I C INTERFACE ■ Ten Bit Address Mask Register (ITMK) Contents Table 21.2-4 Function of Each Bit of the Ten Bit Address Mask Register (ITMK) Bit name Function This bit enables the ten bit slave address (and the acknowledging upon its reception). ENTB: Write access to this bit is only possible if the interface is disabled (EN= 0 in ICCR).
Page 453: C Seven Bit Slave Address Register (Isba)
CHAPTER 21 400 kHz I C INTERFACE 21.2.5 C Seven Bit Slave Address Register (ISBA) This register designates the seven bit slave address. ■ I C Seven Bit Slave Address Register Write access to this register is only possible if the interface is disabled (EN= 0 in ICCR). ISBA Address: SA6 SA5 SA4 SA3 SA2 SA1 SA0...
Page 454 CHAPTER 21 400 kHz I C INTERFACE ■ I C Seven Bit Slave Address Mask Register (ISMK) This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to this register is only possible if the interface is disabled (EN= 0 in ICCR). ISMK Address: ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0...
Page 455: I 2 C Data Register (Idar)
CHAPTER 21 400 kHz I C INTERFACE 21.2.6 C Data Register (IDAR) Data Register for the 400 kHz I C Interface. ■ I C Data Register (IDAR) IDAR Address: D7 D6 D5 D4 D3 D2 D1 D0 0035A8 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W...
Page 456: I 2 C Clock Control Register (Iccr)
CHAPTER 21 400 kHz I C INTERFACE 21.2.7 C Clock Control Register (ICCR) The I C clock control register (ICCR) has the following functions: • Enable test mode • Enable I/O pad noise filters • Enable I C interface operation •...
Page 457 CHAPTER 21 400 kHz I C INTERFACE ■ I C Clock Control Register (ICCR) Contents Table 21.2-8 Function of Each Bit of the I C Clock Control Register Bit name Function bit15 Undefined This bit always returns "0" during reading. This bit enables the noise filters built into the SDA and SCL I/O pads.
Page 458 CHAPTER 21 400 kHz I C INTERFACE ■ Clock Prescaler Settings The calculation formula for CS0 to CS4 is determined as follows: φ Bit rate = n>0 : machine clock, Noise filter disabled n × 12 + 16 φ Bit rate = n>0 : machine clock, Noise filter enabled, INFCR:SEL[1:0] = 01 n ×...
Page 459: Noise Filter Configuration Register (Infcr)
CHAPTER 21 400 kHz I C INTERFACE 21.2.8 Noise Filter Configuration Register (INFCR) The Noise Filter Configuration Register (INFCR) is used to configure the filter time of the SDA and SCL noise filters as a function of the machine clock frequency. It is only available in MB90394HA, MB90V390HA and MB90V390HB.
Page 460: I 2 C Interface Operation
CHAPTER 21 400 kHz I C INTERFACE 21.3 C Interface Operation The I C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial clock line (SCL). The I C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines, enabling wired logic applications.
Page 461 CHAPTER 21 400 kHz I C INTERFACE ■ Slave Address Detection In slave mode, after a start condition is generated the BB is set to "1" and data sent from the master device is received into the IDAR register. After the reception of eight bits, the contents of the IDAR register is compared to the ISBA register using the bit mask stored in ISMK if the ENSB bit in the ISMK register is "1".
Page 462 CHAPTER 21 400 kHz I C INTERFACE ■ Addressing Slaves In master mode, after a start condition is generated the BB and TRX bits are set to "1" and the contents of the IDAR register is sent in MSB first order. After address data is sent and an acknowledge signal was received from the slave device, bit0 of the sent data (bit0 of the IDAR register after sending) is inverted and stored in the TRX bit.
Page 463: Programming Flow Charts
CHAPTER 21 400 kHz I C INTERFACE 21.4 Programming Flow Charts Each programming flow charts for the 400 kHz I C interface is shown below. ■ Programming Flow Charts Figure 21.4-1 Example of Slave Addressing and Sending Data Addressing a 7 bit slave Sending data Start Start...
Page 464 CHAPTER 21 400 kHz I C INTERFACE Figure 21.4-2 Example of Receiving Data Start Address slave for read Clear ACK bit in IBCR if it’s the last byte to read from slave; INT := 0 INT=1? YES Bus error BER=1? reenable IF Last byte transferred?
Page 465: Chapter 22 Serial I/O
CHAPTER 22 SERIAL I/O This chapter explains the functions and operations of the serial I/O. 22.1 Outline of Serial I/O 22.2 Serial I/O Registers 22.3 Serial I/O Prescaler (CDCR) 22.4 Serial I/O Operation...
Page 466: Outline Of Serial I/O
CHAPTER 22 SERIAL I/O 22.1 Outline of Serial I/O The serial I/O interface operates in two modes: • Internal shift clock mode: Data is transferred in synchronization with the internal clock. • External shift clock mode: Data is transferred in synchronization with the clock supplied via the external pin (SCK4).
Page 467: Serial I/O Registers
CHAPTER 22 SERIAL I/O 22.2 Serial I/O Registers The serial I/O has the following two registers: • Serial mode control status register (SMCS) • Serial data register (SDR) ■ Serial I/O Registers Serial mode control Address : 00002D SMD2 SMD1 SMD0 BUSY STOP STRT...
Page 468: Serial Mode Control Status Register (Smcs)
CHAPTER 22 SERIAL I/O 22.2.1 Serial Mode Control Status Register (SMCS) The serial mode control status register (SMCS) controls the serial I/O transfer mode. ■ Upper Byte of Serial Mode Control Status Register (SMCS) Figure 22.2-1 Configuration of the Serial Mode Control Status Register (Upper Byte) bit15 bit14 bit13...
Page 469 CHAPTER 22 SERIAL I/O ■ Lower Byte of Serial Mode Control Status Register (SMCS) Figure 22.2-2 Configuration of the Serial Mode Control Status Register (Lower Byte) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address Initial value MODE SCOE 00002C XXXX0000 SCOE Shift Clock Output Enable bit...
Page 470 CHAPTER 22 SERIAL I/O ■ Bit Functions of Serial Mode Control Status Register (SMCS) Table 22.2-1 Bit Functions of Serial Mode Control Status Register Bit name Function SMD2 to SMD0: bit15 to Shift clock mode Shift Clock Mode selection bits, see Table 22.2-2. bit13 selection bits SIE:...
Page 471 CHAPTER 22 SERIAL I/O ■ Shift Clock Selection The Shift Clock Mode Selection bits are used to select the serial shift clock mode, as shown in Table 22.2- 2. The second part is related to the Serial I/O prescaler register (CDCR). For details, see Section "22.3 Serial I/O Prescaler (CDCR)".
Page 472: Serial Shift Data Register (Sdr)
CHAPTER 22 SERIAL I/O 22.2.2 Serial Shift Data Register (SDR) This serial shift data register stores the serial I/O transfer data. During transfer, the SDR must not be read or written to. ■ Serial Shift Data Register (SDR) Initial value Address : 00002E XXXXXXXX R/W : Readable and writable...
Page 473: Serial I/O Prescaler (Cdcr)
CHAPTER 22 SERIAL I/O 22.3 Serial I/O Prescaler (CDCR) The Serial I/O Prescaler provides the shift clock for the Serial I/O. The operation clock for the Serial I/O is obtained by dividing the machine clock. The Serial I/O is designed so that a constant baud rate can be obtained for a variety of machine clocks by the use of the communication prescaler.
Page 474: Serial I/O Operation
CHAPTER 22 SERIAL I/O 22.4 Serial I/O Operation The extended serial I/O consists of the serial mode control status register (SMCS) and shift register (SDR), and is used for input and output of 8-bit serial data. ■ Serial I/O Operation The bits in the shift register are serially output via the serial output pin (SOT4 pin) at the falling edge of the serial shift clock (external clock or internal clock).
Page 475: Shift Clock
CHAPTER 22 SERIAL I/O 22.4.1 Shift Clock There are two modes of shift clock: internal or external shift clock. These two modes are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit. ■...
Page 476: Serial I/O Operation
CHAPTER 22 SERIAL I/O 22.4.2 Serial I/O Operation There are four serial I/O operation statuses: • STOP • Halt • SDR Read/Write standby • Transfer ■ Serial I/O Operation ● STOP The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift counter is initialized, and "0"...
Page 477 CHAPTER 22 SERIAL I/O Figure 22.4-1 Extended I/O Serial Interface Operation Transitions Reset STOP=0 & STRT=0 End of transfer STOP STRT=0, BUSY=0 STRT=0, BUSY=0 STOP=1 MODE=0 MODE=0 STOP=0 & & STOP=0 STOP=1 STOP=1 STOP=0 STRT=1 & & STRT=1 Transfer Serial data register Read/Write standby MODE=1 &...
Page 478: Shift Operation Start/Stop Timing
CHAPTER 22 SERIAL I/O 22.4.3 Shift Operation Start/Stop Timing To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS. The system may stop the shift operation at the end of transfer or when "1" is set in the STOP bit.
Page 479 CHAPTER 22 SERIAL I/O ● External shift clock mode with instruction shift (LSB first) Figure 22.4-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift) SCK=0 in PDR SCK=0 in PDR SCK4 SCK=1 in PDR (Transfer end) STRT If MODE=0 BUSY DO7 (Data maintained)
Page 480 CHAPTER 22 SERIAL I/O Figure 22.4-7 Serial Data I/O Shift Timing ❍ LSB first (When the BDS bit is "0") SCK4 SIN Input SIN4 SOT Output SOT4 ❍ MSB first (When the BDS bit is "1") SCK4 SIN Input SIN4 SOT Output SOT4...
Page 481: Interrupt Function Of The Extended Serial I/O Interface
CHAPTER 22 SERIAL I/O 22.4.4 Interrupt Function of the Extended Serial I/O Interface This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of SMCS, an interrupt request is issued to the CPU.
Page 482 CHAPTER 22 SERIAL I/O...
Page 483: Chapter 23 Can Controller
This chapter explains the functions and operations of the CAN controller. Note: CAN controller 2 to 4 are not specified in the MB90390 series. For this reason Fujitsu recommends not to use these features. 23.1 Features of CAN Controller 23.2 Block Diagram of CAN Controller 23.3 List of Overall Control Registers...
Page 484: Features Of Can Controller
CHAPTER 23 CAN CONTROLLER 23.1 Features of CAN Controller The CAN controller is a module built into a 16-bit microcontroller (F MC-16LX). The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. ■...
Page 485: Block Diagram Of Can Controller
CHAPTER 23 CAN CONTROLLER 23.2 Block Diagram of CAN Controller Figure 23.2-1 shows a block diagram of the CAN controller. ■ Block Diagram of CAN Controller Figure 23.2-1 Block Diagram of CAN Controller TQ (Operating clock) MC-16LX bus Prescaler Clock Bit timing generation SYNC, TSEG1, TSEG2 1 to 64 frequency division...
Page 486: List Of Overall Control Registers
CHAPTER 23 CAN CONTROLLER 23.3 List of Overall Control Registers Table 23.3-1 lists overall control registers. ■ List of Overall Control Registers Table 23.3-1 List of Overall Registers (1/2) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 CAN3 CAN4 000070 000080 003570...
Page 487 003D18 003F18 XXXXXXXX XXXXXXXX 003719 003919 003B19 003D19 003F19 Acceptance mask AMR1 register 1 00371A 00391A 003B1A 003D1A 003F1A XXXXX--- XXXXXXXX 00371B 00391B 003B1B 003D1B 003F1B *: CAN2, CAN3, CAN4 are not supported in all devices of the MB90390 series...
Page 488: List Of Message Buffers (Id Registers)
CHAPTER 23 CAN CONTROLLER 23.4 List of Message Buffers (ID Registers) Table 23.4-1 lists message buffers (ID registers). ■ List of Message Buffers (ID Registers) Table 23.4-1 List of Message Buffers (ID Registers) (1/3) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2...
Page 489 CHAPTER 23 CAN CONTROLLER Table 23.4-1 List of Message Buffers (ID Registers) (2/3) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 CAN3 CAN4 003638 003838 003A38 003C38 003E38 XXXXXXXX XXXXXXXX 003639 003839 003A39 003C39 003E39 ID register 6 IDR6 00363A 00383A 003A3A...
Page 490 003A5C 003C5C 003E5C XXXXXXXX XXXXXXXX 00365D 00385D 003A5D 003C5D 003E5D ID register 15 IDR15 00365E 00385E 003A5E 003C5E 003E5E XXXXX--- XXXXXXXX 00365F 00385F 003A5F 003C5F 003E5F *: CAN2, CAN3, CAN4 are not supported in all devices of the MB90390 series...
Page 491: List Of Message Buffers (Dlc Registers And Data Registers)
CHAPTER 23 CAN CONTROLLER 23.5 List of Message Buffers (DLC Registers and Data Registers) Table 23.5-1 lists message buffers (DLC registers) and message buffers (data registers). ■ List of Message Buffers (DLC Registers and Data Registers) Table 23.5-1 List of Message Buffers (DLC Registers and Data Register) (1/3) Address Register Abbreviation...
Page 492 CHAPTER 23 CAN CONTROLLER Table 23.5-1 List of Message Buffers (DLC Registers and Data Register) (2/3) Address Register Abbreviation Access Initial Value CAN0 CAN1 CAN2 CAN3 CAN4 00367A 00387A 003A7A 003C7A 003E7A ----XXXX DLC register 13 DLCR13 00367B 00387B 003A7B 003C7B 003E7B 00367C...
Page 493 DTR14 bytes) 0036F7 0038F7 003AF7 003CF7 003EF7 XXXXXXXX 0036F8 0038F8 003AF8 003CF8 003EF8 XXXXXXXX Data register 15 (8 DTR15 bytes) 0036FF 0038FF 003AFF 003CFF 003EFF XXXXXXXX *: CAN2, CAN3, CAN4 are not supported in all devices of the MB90390 series...
Page 494: Classifying The Can Controller Registers
CHAPTER 23 CAN CONTROLLER 23.6 Classifying the CAN Controller Registers There are three types of CAN controller registers: • Overall control registers • Message buffer control registers • Message buffers ■ Overall Control Registers The overall control registers are the following four registers: •...
Page 495: Control Status Register (Csr)
CHAPTER 23 CAN CONTROLLER 23.6.1 Control Status Register (CSR) The lower 8 bits with the CAN control status register (CSR) is prohibited from executing any bit manipulation instructions (Read-Modify-Write (RMW) instructions). Only in the case of HALT bits unchanged, use any bit manipulation instructions without problems (initialization of the macro instructions, etc.).
Page 496 CHAPTER 23 CAN CONTROLLER ■ Control Status Register (CSR-lower) Contents Table 23.6-1 Function of Each Bit of the Control Status Register (Lower) Bit name Function Writing "1" to this bit switches from a general-purpose port pin to a transmit pin of the TOE: CAN controller.
Page 497 CHAPTER 23 CAN CONTROLLER ■ Control Status Register (CSR) (Upper) Figure 23.6-2 Configuration of the Control Status Register (Upper Byte) CSR0/CSR1/CSR2/CSR3/CSR4 (upper Address: CAN0: 003701 Initial value CAN1: 003901 0 0 X X X 0 0 0 CAN2: 003B01 CAN3: 003D01 CAN4: 003F01 bit 8 Node Status bit...
Page 498 CHAPTER 23 CAN CONTROLLER ■ Control Status Register (CSR-upper) Contents Table 23.6-2 Function of Each Bit of the Control Status Register (Upper) Bit name Function This bit indicates whether a message is being transmitted. "0": Message not being transmitted bit15 Transmit status "1": Message being transmitted This bit is "0"...
Page 499 CHAPTER 23 CAN CONTROLLER Table 23.6-3 Correspondence between NS1 and NS0 and Node Status Node Status Error active Warning (error active) Error passive Bus off Note: Warning (error active) is included in the error active in CAN Specification 2.0B for the node status, however, indicates that the transmit error counter or receive error counter has exceeded 96.
Page 500: Bus Operation Stop Bit (Halt = 1)
CHAPTER 23 CAN CONTROLLER 23.6.2 Bus Operation Stop Bit (HALT = 1) The bus operation stop bit sets or cancels stopping of bus operation, or indicates its status. ■ Conditions for Setting Bus Operation Stop (HALT=1) There are three conditions for setting bus operation stop (HALT = 1): •...
Page 501 CHAPTER 23 CAN CONTROLLER ■ State during Bus Operation Stop (HALT = 1) • The bus does not perform any operation, such as transmission and reception. • The transmit output pin (TX) outputs a "H" level (recessive bit). • The values of other registers and error counters are not changed. Note: The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
Page 502: Last Event Indicator Register (Leir)
CHAPTER 23 CAN CONTROLLER 23.6.3 Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to "1", other bits are set to 0s. ■...
Page 503 CHAPTER 23 CAN CONTROLLER ■ Last Event Indicator Register (LEIR) Contents Table 23.6-4 Function of Each Bit of the Last Event Indicator Register Bit name Function When this bit is "1", node status transition is the last event. This bit is set to "1" at the same time the NT bit of the control status register (CSR) is NTE: set.
Page 504: Receive And Transmit Error Counters (Rtec)
CHAPTER 23 CAN CONTROLLER 23.6.4 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read. ■ Receive and Transmit Error Counters (RTEC) Figure 23.6-5 Configuration of the Receive and Transmit Error Counters Address: RTEC (upper)
Page 505: Bit Timing Register (Btr)
CHAPTER 23 CAN CONTROLLER 23.6.5 Bit Timing Register (BTR) Bit timing register (BTR) stores the prescaler and bit timing setting. ■ Bit Timing Register (BTR) Figure 23.6-6 Configuration of the Bit Timing Register (BTR) Address: BTR (upper) CAN0: 003707 TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0 Initial value CAN1: 003907 CAN2: 003B07...
Page 506 CHAPTER 23 CAN CONTROLLER ■ Prescaler Settings Figure 23.6-7 shows the bit time segment in CAN specification, Figure 23.6-8 shows the bit time segment in CAN controller. Figure 23.6-7 Bit Time Segment in CAN Specification Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample point Figure 23.6-8 Bit Time Segment in CAN Controller...
Page 507: Message Buffer Valid Register (Bvalr)
CHAPTER 23 CAN CONTROLLER 23.6.6 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) stores the validity of the message buffers or displays their state. ■ Message Buffer Valid Register (BVALR) Figure 23.6-9 Configuration of the Message Buffer Valid Register (BVALR) Address: BVALRn (upper) CAN0: 000071...
Page 508: Ide Register (Ider)
CHAPTER 23 CAN CONTROLLER 23.6.7 IDE register (IDER) This register stores the frame format used by the message buffers (x) during transmission/reception. ■ IDE Register (IDER) Figure 23.6-10 Configuration of the IDE Register (IDER) Address: IDERn(upper) CAN0: 003709 IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 IDE9 IDE8 Initial value CAN1: 003909 CAN2: 003B09...
Page 509: Transmission Request Register (Treqr)
CHAPTER 23 CAN CONTROLLER 23.6.8 Transmission Request Register (TREQR) Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state. ■ Transmission Request Register (TREQR) Figure 23.6-11 Configuration of the Transmission Request Register (TREQR) Address: TREQRn (upper) CAN0: 000073 TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8...
Page 510: Transmission Rtr Register (Trtrr)
CHAPTER 23 CAN CONTROLLER 23.6.9 Transmission RTR Register (TRTRR) This register stores the RTR (Remote Transmission Request) bits for the message buffers (x). ■ Transmission RTR Register (TRTRR) Figure 23.6-12 Configuration of the Transmission RTR Register (TRTRR) Address: TRTRRn (upper) CAN0: 00370B TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8 Initial value...
Page 511: Remote Frame Receiving Wait Register (Rfwtr)
CHAPTER 23 CAN CONTROLLER 23.6.10 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) stores the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is "1" and TRTRx of the transmitting RTR register (TRTRR) is "0").
Page 512: Transmission Cancel Register (Tcanr)
CHAPTER 23 CAN CONTROLLER 23.6.11 Transmission Cancel Register (TCANR) When "1" is written to TCANx, this register cancels a pending request for transmission to the message buffer (x). At completion of cancellation, TREQx of the transmission request register (TREQR) becomes "0". Writing "0" to TCANx is ignored. This is a write only register and its read value is always "0".
Page 513: Transmission Complete Register (Tcr)
CHAPTER 23 CAN CONTROLLER 23.6.12 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes "1". If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt occurs. ■ Transmission Complete Register (TCR) Figure 23.6-15 Configuration of the Transmission Complete Register (TCR) Address: TCRn (upper)
Page 514: Transmission Interrupt Enable Register (Tier)
CHAPTER 23 CAN CONTROLLER 23.6.13 Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is "1"). ■...
Page 515: Reception Complete Register (Rcr)
CHAPTER 23 CAN CONTROLLER 23.6.14 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes "1". If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt occurs. ■ Reception Complete Register (RCR) Figure 23.6-17 Configuration of the Reception Complete Register (RCR) Address: RCRn (upper)
Page 516: Remote Request Receiving Register (Rrtrr)
CHAPTER 23 CAN CONTROLLER 23.6.15 Remote Request Receiving Register (RRTRR) After a remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the same time as RCx setting to "1"). ■ Remote Request Receiving Register (RRTRR) Figure 23.6-18 Configuration of the Remote Request Receiving Register (RRTRR) Address: RRTRRn (upper) CAN0: 00007B...
Page 517: Receive Overrun Register (Rovrr)
CHAPTER 23 CAN CONTROLLER 23.6.16 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is "1" when completing storing of a received message in the message buffer (x), ROVRx becomes "1", indicating that reception has overrun. ■ Receive Overrun Register (ROVRR) Figure 23.6-19 Configuration of the Receive Overrun Register (ROVRR) Address: ROVRRn (upper)
Page 518: Reception Interrupt Enable Register (Rier)
CHAPTER 23 CAN CONTROLLER 23.6.17 Reception Interrupt Enable Register (RIER) Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is "1"). ■...
Page 519: Acceptance Mask Select Register (Amsr)
CHAPTER 23 CAN CONTROLLER 23.6.18 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the received message ID’s and the message buffer ID’s. ■ Acceptance Mask Select Register (AMSR) Figure 23.6-21 Configuration of the Acceptance Mask Select Register (AMSR) Address: AMSRn Byte 0 CAN0: 003710...
Page 520 CHAPTER 23 CAN CONTROLLER Table 23.6-7 Selection of Acceptance Mask AMSx.1 AMSx.0 Acceptance Mask Full-bit comparison Full-bit mask Acceptance mask register 0 (AMR0) Acceptance mask register 1 (AMR1) Notes: • AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is "0").
Page 521: Acceptance Mask Registers 0 And 1 (Amr0 And Amr1)
CHAPTER 23 CAN CONTROLLER 23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) There are two acceptance mask registers, AMR0 and AMR1, both of which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
Page 522 CHAPTER 23 CAN CONTROLLER Figure 23.6-23 Configuration of the Acceptance Mask Register 1 (AMR1) Address: AMR1n Byte 0 CAN0: 003718 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 Initial value CAN1: 003918 CAN2: 003B18 X X X X X X X X CAN3: 003D18 R/W R/W R/W R/W R/W R/W...
Page 523: Message Buffers
CHAPTER 23 CAN CONTROLLER 23.6.20 Message Buffers There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). ■ Message Buffers ● The message buffer (x) is used both for transmission and reception. ●...
Page 524: Id Register X (X = 0 To 15) (Idrx)
CHAPTER 23 CAN CONTROLLER 23.6.21 ID Register x (x = 0 to 15) (IDRx) ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x). ■ ID Register x (x = 0 to 15) (IDRx) Figure 23.6-24 Configuration of the ID Registers (IDRx) Address: IDRxn Byte 0...
Page 525 CHAPTER 23 CAN CONTROLLER When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0.
Page 526: Dlc Register X (X = 0 To 15) (Dlcrx)
CHAPTER 23 CAN CONTROLLER 23.6.22 DLC Register x (x = 0 to 15) (DLCRx) DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x. ■ DLC Register x (x = 0 to 15) (DLCRx) Figure 23.6-25 Configuration of the DLC Registers (DLCRx) Address: DLCRnx (lower)
Page 527: Data Register X (X = 0 To 15) (Dtrx)
CHAPTER 23 CAN CONTROLLER 23.6.23 Data Register x (x = 0 to 15) (DTRx) Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame.
Page 528 CHAPTER 23 CAN CONTROLLER ● Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB first. ● Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB first. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined.
Page 529: Transmission Of Can Controller
CHAPTER 23 CAN CONTROLLER 23.7 Transmission of CAN Controller When "1" is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and TCx of the transmission complete register (TCR) becomes "0". ■...
Page 530 CHAPTER 23 CAN CONTROLLER Note: The transmission request is canceled by storing either data frames or remote frames. ■ Completing Transmission of the CAN Controller When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the transmission complete register (TCR) becomes "1".
Page 531 CHAPTER 23 CAN CONTROLLER ■ Transmission Flowchart of the CAN Controller Figure 23.7-1 Transmission Flowchart of the CAN Controller Transmission request (TREQx := 1) TCx := 0 TREQx? RFWTx? RRTRx? If there are any other message buffers meeting the above conditions, select the lowest-numbered message buffer.
Page 532: Reception Of Can Controller
CHAPTER 23 CAN CONTROLLER 23.8 Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. ■ Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is "0").
Page 533 CHAPTER 23 CAN CONTROLLER Figure 23.8-1 shows the flowchart determining message buffer (x) where received messages stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits Mask.
Page 534 CHAPTER 23 CAN CONTROLLER ■ Completing Reception RCx of the reception complete register (RCR) becomes "1" after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself.
Page 535: Reception Flowchart Of Can Controller
CHAPTER 23 CAN CONTROLLER 23.9 Reception Flowchart of CAN Controller Figure 23.9-1 shows a reception flowchart of the CAN controller. ■ Reception Flowchart of the CAN Controller Figure 23.9-1 Reception Flowchart of the CAN Controller Detection of start of data frame or remote frame (SOF) Is any message buffer (x) passing to the acceptance filter found?
Page 536: 23.10 How To Use The Can Controller
CHAPTER 23 CAN CONTROLLER 23.10 How to Use the CAN Controller The following settings are required to use the CAN controller: • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode ■ Setting Bit Timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is"...
Page 537 CHAPTER 23 CAN CONTROLLER ■ Setting Low-power Consumption Mode To set the F MC-16LX in a low-power consumption mode (Stop and Time-base timer), write "1" to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1).
Page 538: Procedure For Transmission By Message Buffer (X)
CHAPTER 23 CAN CONTROLLER 23.11 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to activate the message buffer (x). ■ Procedure for Transmission by Message Buffer (x) ●...
Page 539 CHAPTER 23 CAN CONTROLLER ● Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to "0" to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is "1"...
Page 540: Procedure For Reception By Message Buffer (X)
CHAPTER 23 CAN CONTROLLER 23.12 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. ■ Procedure for Reception by Message Buffer (x) ● Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1".
Page 541 CHAPTER 23 CAN CONTROLLER Figure 23.12-1 Example of Receive Interrupt Handling Interrupt with RCx = 1 Read received messages. A: = ROVRx ROVRx := 0 A = 0? RCx := 0...
Page 542: 23.13 Setting Configuration Of Multi-Level Message Buffer
CHAPTER 23 CAN CONTROLLER 23.13 Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID’s of messages are received, in other words, if there is insufficient time for handling messages, more than one message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU.
Page 543 CHAPTER 23 CAN CONTROLLER Figure 23.13-1 Examples of Operation of Multi-level Message Buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 . . . AM28 to AM18 Select AMR0. AMS0 0000 1111 111 RC15, RC14, RC13 ID28 to ID18 ..
Page 544: 23.14 Setting The Redirection Of Can1 And Can3 Rx/Tx Pin
CHAPTER 23 CAN CONTROLLER 23.14 Setting the redirection of CAN1 and CAN3 RX/TX pin CAN1 and CAN3 can be changed the redirection CAN1 RX/TX pin (RX1/TX1) to RX0/TX0 pin and CAN3 RX/TX pin (RX3/TX3) to RX2/TX2 pin by the CANSWR register. ■...
Page 545 CHAPTER 23 CAN CONTROLLER Figure 23.14-2 Redirection of CAN1 and CAN3 RX/TX CAN0 CAN0 switched by TXS01 switched by RXS01 of CANSWR of CANSWR CAN1 CAN1 CAN2 CAN2 switched by TXS23 switched by RXS23 of CANSWR of CANSWR CAN3 CAN3...
Page 546: 23.15 Setting The Can Direct Mode Register
CHAPTER 23 CAN CONTROLLER 23.15 Setting the CAN Direct Mode Register The MB90390 series provides a clock modulator for the system clock. Since the CAN controller is not able to operate with a modulated clock, the unmodulated clock is provided to the CAN controller independently from the clock modulator settings.
Page 547: 23.16 Precautions When Using Can Controller
CHAPTER 23 CAN CONTROLLER 23.16 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. ■ For -H Devices, e.q. MB90F394H and MB90V390H: Caution for Disabling Message Buffers by BVAL Bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is "0"...
Page 548 CHAPTER 23 CAN CONTROLLER ■ For Non-H Devices, e.q. MB90V390: Caution for Disabling Message Buffers by BVAL Bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN Controller is ready to receive or transmit messages).
Page 549: Chapter 24 Stepping Motor Controller
CHAPTER 24 STEPPING MOTOR CONTROLLER This chapter explains the functions and operations of the stepping motor controller. 24.1 Outline of Stepping Motor Controller 24.2 Stepping Motor Controller Registers 24.3 Notes on Using the Stepping Motor Controller...
Page 550: Outline Of Stepping Motor Controller
The combination of the PWM Pulse Generators and Selector Logic is designed to control the rotation of the motor. A Synchronization mechanism assures the synchronous operations of the two PWMs. The MB90390 series provides 6 separate Stepping Motor Controllers.
Page 551: Stepping Motor Controller Registers
CHAPTER 24 STEPPING MOTOR CONTROLLER 24.2 Stepping Motor Controller Registers The stepping motor controller "n" has the following five types of registers: • PWM control n register (PWCn) • PWM1 compare n register (PWC1n) • PWM2 compare n register (PWC2n) •...
Page 552: Pwm Control 0 Register
CHAPTER 24 STEPPING MOTOR CONTROLLER 24.2.1 PWM Control 0 register The PWM control 0 register starts and stops the stepping motor controller, controls interrupts, and sets the external output pins. Its function is equal to all other SMC modules. ■ PWM Control 0 Register Figure 24.2-2 Configuration of the PWM Control 0 Register Address: PWCn...
Page 553 CHAPTER 24 STEPPING MOTOR CONTROLLER ■ Pulse Width Control Register Contents Table 24.2-1 Function of Each Bit of Pulse Width Control Register (PWCn) Bit name Function OE2: When this bit is set to "1", the external pins are assigned as PWM2Pn and PWM2Mn bit7 Output enable 2 bit outputs.
Page 554: Pwm1 And Pwm2 Compare Registers
CHAPTER 24 STEPPING MOTOR CONTROLLER 24.2.2 PWM1 and PWM2 Compare Registers The contents of the two 8-bit compare registers determine the widths of PWM pulses. The stored value of "00 " represents the PWM duty of 0% and "FF " represents the duty of 99.6%.
Page 555: Pwm1 And Pwm2 Select Registers
CHAPTER 24 STEPPING MOTOR CONTROLLER 24.2.3 PWM1 and PWM2 Select Registers The PWM1 and PWM2 select registers "0", "1", the PWM pulse, or high impedance for the external pin output of the stepping motor controller. ■ PWM1 Select Registers Figure 24.2-5 Configuration of the PWM1 Select Registers Address: PWS1n SMC0: 003552...
Page 556 CHAPTER 24 STEPPING MOTOR CONTROLLER ■ Pulse Width Modulator 1 Select Registers (PWS1n) Contents Table 24.2-2 Function of Each Bit of the PWM1 Select Registers Bit name Function − bit7, bit6 Undefined These bits selects the output signal at PWM1Pn PWM1Pn P2 to P0: "L"...
Page 557 CHAPTER 24 STEPPING MOTOR CONTROLLER ■ PWM2 Select Registers Address: PWS2n SMC0: 003553 SMC1: 003557 P1 P0 M2 M1 M0 Initial value SMC2: 00355B X 0 0 0 0 0 0 0 SMC3: 00355F R/W R/W R/W R/W R/W SMC4: 003563 SMC5: 003567 bit 10 bit 9...
Page 558 CHAPTER 24 STEPPING MOTOR CONTROLLER ■ Pulse Width Modulator 2 Select Registers (PWS2n) Contents Table 24.2-3 Function of Each Bit of the PWM 2 Select Registers Bit name Function − bit15 Undefined This bit is prepared to synchronize the settings for the PWM outputs. Any modifications in the two compare registers and two select registers are not reflected to the output signals until this bit is set.
Page 559: Notes On Using The Stepping Motor Controller
CHAPTER 24 STEPPING MOTOR CONTROLLER 24.3 Notes on Using the Stepping Motor Controller This section provides notes on using the stepping motor controller ■ Notes on Changing the PWM Setting Values PWM Compare Register 1 (PWC1n), PWM Compare Register 2 (PWC2n), PWM Selection Register 1 (PWS1n), and PWM Selection Register 2 (PWS2n) can always be accessed.
Page 560 CHAPTER 24 STEPPING MOTOR CONTROLLER...
Page 561: Chapter 25 Sound Generator
CHAPTER 25 SOUND GENERATOR This chapter explains the functions and operations of the sound generator. 25.1 Outline of Sound Generator 25.2 Sound Generator Registers...
Page 562: Outline Of Sound Generator
CHAPTER 25 SOUND GENERATOR 25.1 Outline of Sound Generator The Sound Generator consists of the Sound Control register, Frequency Data register, Amplitude Data register, Decrement Grade register, Tone Count register, PWM pulse generator, Frequency counter, Decrement counter and Tone Pulse counter. ■...
Page 563: Sound Generator Registers
CHAPTER 25 SOUND GENERATOR 25.2 Sound Generator Registers The sound generator has the following five types of registers: • Sound control register (SGCR) • Frequency data register (SGFR) • Amplitude data register (SGAR) • Decrement grade register (SGDR) • Tone count register (SGTR) ■...
Page 564: Sound Generator Control Register
CHAPTER 25 SOUND GENERATOR 25.2.1 Sound Generator Control Register The sound control register controls the operation status of the sound generator by controlling interrupts and setting the external output pins. ■ Sound Generator Control Register (Lower) Figure 25.2-2 Configuration of the Sound Generator Control Register (Lower Byte) SGCR (lower) Address: S0 TONE OE2...
Page 565 CHAPTER 25 SOUND GENERATOR ■ Sound Generator Control Register (SGCR) (Lower) Contents Table 25.2-1 Function of Each Bit of the Sound Control Register (Lower) Bit name Function These bits specify the clock input signal for the Sound Generator. Clock input Machine clock S1, S0: bit7, bit6...
Page 566 CHAPTER 25 SOUND GENERATOR ■ Sound Generator Control Register (Upper) Figure 25.2-3 Configuration of the Sound Generator Control Register (Upper Byte) SGCR (upper) 00005F Reserved BUSY DEC Initial value 0 X X X X X 0 0 R R/W bit 8 Auto-decrement enable bit Auto-decrement disabled Auto-decrement enabled...
Page 567: Frequency Data Register
CHAPTER 25 SOUND GENERATOR 25.2.2 Frequency Data register The Frequency Data register stores the reload value for the Frequency counter. The stored value represents the frequency of the sound (or the tone signal from the toggle flip-flop). The register value is reloaded into the counter at Frequency counter underflow and PWM pulse generator underflow.
Page 568: Amplitude Data Register
CHAPTER 25 SOUND GENERATOR 25.2.3 Amplitude Data Register The Amplitude Data register stores the reload value for the PWM pulse generator. The register value represents the amplitude of the sound. The register value is reloaded into the PWM pulse generator at falling edge of tone signal. ■...
Page 569: Decrement Grade Register
CHAPTER 25 SOUND GENERATOR 25.2.4 Decrement Grade Register The Decrement Grade register stores the reload value for the Decrement counter. They are prepared to automatically decrement the stored value in the Amplitude Data register. The register value is reloaded into the counter at Decrement counter underflow and falling edge of tone signal.
Page 570: Tone Count Register
CHAPTER 25 SOUND GENERATOR 25.2.5 Tone Count Register The Tone Count register stores the reload value for the Tone Pulse counter. The Tone Pulse counter accumulate the number of tone pulses (or number of decrement operations) and when it reaches the reload value it sets the INT bit. They are intended to reduce the frequency of interrupts.
Page 571: Chapter 26 Address Match Detection Function
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and operation. 26.1 Outline of the Address Match Detection Function 26.2 Registers of the Address Match Detection Function 26.3 Operation of the Address Match Detection Function 26.4 Example of the Address Match Detection Function...
Page 572: Outline Of The Address Match Detection Function
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION 26.1 Outline of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code (01 Consequently, the CPU executes the INT9 instruction when executing a specified instruction.
Page 573: Registers Of The Address Match Detection Function
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION 26.2 Registers of the Address Match Detection Function The two types of registers for the address match detection function are as follows: • Program address detection registers (PADR0, PADR1, PADR3 to PADR5) • Program address detection control status register (PACSR0 and PACSR1) ■...
Page 574 CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION ■ Program Address Detection Control Status Register (PACSR) The program address detection control / status register (PACSR) controls the operation of the address detection function. Figure 26.2-2 Program Address Detection Control Status Registers (PACSR0/PACSR1) Address: PACSR0 00009E...
Page 575: Operation Of The Address Match Detection Function
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION 26.3 Operation of the Address Match Detection Function If the program counter specifies the same address as the address match detection register, the INT9 instruction is executed. The address match detection function can be achieved by processing the INT9 instruction routine.
Page 576: Example Of The Address Match Detection Function
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION 26.4 Example of the Address Match Detection Function Figure 26.4-1 shows a system configuration example of the address match detection function. Table 26.4-1 lists the E PROM memory map. ■ System Configuration Example of the Address Match Detection Function Figure 26.4-1 System Configuration Example of the Address Match Detection Function PROM MC-16LX...
Page 577 CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION ● When a program error occurs: The main body of the patch program and program address are transferred to the MCU through the connector (UART). The MCU writes the information to E PROM. ● Reset sequence The MCU reads the value of E PROM after reset.
Page 578 CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION Figure 26.4-3 Flow of Program Patch Processing Reset Reads "00 " of E PROM INT9 "0000 " (E PROM)=0 To patch program JMP 000400H Read address "0001 " to "0003 " (E PROM) Execute patch program PADR0 (MCU) "000400 "...
Page 579: Chapter 27 Rom Mirroring Module
CHAPTER 27 ROM MIRRORING MODULE This chapter explains the ROM mirroring module. 27.1 Outline of ROM Mirroring Module 27.2 ROM Mirroring Register (ROMM)
Page 580: Outline Of Rom Mirroring Module
CHAPTER 27 ROM MIRRORING MODULE 27.1 Outline of ROM Mirroring Module The ROM Mirroring module switches whether to mirror the image of the FF bank of the ROM to the 00 bank. ■ Block Diagram of ROM Mirroring Module Figure 27.1-1 Block Diagram of ROM Mirroring Module MC-16LX BUS ROM Mirrroring Register Address Area...
Page 581: Rom Mirroring Register (Romm)
CHAPTER 27 ROM MIRRORING MODULE 27.2 ROM Mirroring Register (ROMM) Do not access the ROM mirroring register (ROMM) when addresses "004000 " to "00FFFF " are being accessed. ■ ROM Mirroring Register (ROMM) Figure 27.2-1 ROM Mirroring Register (ROMM) ROMM Address: Initial value MS MI...
Page 582 CHAPTER 27 ROM MIRRORING MODULE...
Page 583: Chapter 28 3M-Bit Flash Memory
CHAPTER 28 3M-BIT FLASH MEMORY This chapter explains the functions and operation of the 3M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer •...
Page 584: Overview Of 3M-Bit Flash Memory
CHAPTER 28 3M-BIT FLASH MEMORY 28.1 Overview of 3M-bit Flash Memory The 3M-bit flash memory is mapped to the F8/F9 to FF bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and program- access from the CPU in the same way as mask ROM.
Page 585: Block Diagram Of The Entire Flash Memory And Sector Configuration Of The Flash Memory
CHAPTER 28 3M-BIT FLASH MEMORY 28.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory Figure 28.2-1 shows the block diagram of the entire flash memory. Figure 28.2-2 shows the sector configuration of the 3M-bit flash memory. ■...
Page 586 CHAPTER 28 3M-BIT FLASH MEMORY ■ Sector Configuration of the 3M-bit Flash Memory Figure 28.2-2 shows the sector configuration of the 3M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. Figure 28.2-2 Sector Configuration of the 3M-bit Flash Memory Writer MB90F394H(A) CPU address...
Page 587: Write/Erase Modes
CHAPTER 28 3M-BIT FLASH MEMORY 28.3 Write/Erase Modes The flash memory can be accessed in two different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus.
Page 588 CHAPTER 28 3M-BIT FLASH MEMORY Table 28.3-1 Flash Memory Control Signals MB90F394H(A) MBM29LV200 Pin number Normal function Flash memory mode AQ16 AQ17 AQ18 BYTE BYTE RY/BY RY/BY 9 to 12 P40 to P43 AQ8 to AQ11 A7 to A10 18, 19 P46, P47 AQ12, AQ13 A11, A12...
Page 589: Flash Memory Control Status Register (Fmcs)
CHAPTER 28 3M-BIT FLASH MEMORY 28.4 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory. ■ Flash Memory Control Status Register (FMCS) Figure 28.4-1 Flash Memory Control Status Register (FMCS) Initial value Address: 0000AE...
Page 590 CHAPTER 28 3M-BIT FLASH MEMORY [bit4] RDY (ready) This bit enables flash memory write/erase. Flash memory write/erase is disabled while this bit is "0". However, Suspend commands, such as the Read/Reset command and Sector Erase Suspend command, can be accepted even if this bit is "0". •...
Page 591: Starting The Flash Memory Automatic Algorithm
CHAPTER 28 3M-BIT FLASH MEMORY 28.5 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled for sector erase. ■...
Page 592 CHAPTER 28 3M-BIT FLASH MEMORY The Auto-select command shown in Table 28.5-1 is used to know the state of sector protection. When using the Auto-select command, set the address as follows. Table 28.5-2 Address Setting at Auto-select AQ13 to AQ18 DQ7 to DQ0 Sector protection Sector Address...
Page 593: Confirming The Automatic Algorithm Execution State
CHAPTER 28 3M-BIT FLASH MEMORY 28.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences.
Page 594 CHAPTER 28 3M-BIT FLASH MEMORY Table 28.6-2 Hardware Sequence Flag Functions State → → → → → → Write Write completed (write Toggle address specified) DATA:7 DATA:6 DATA:5 DATA:3 DATA:2 → → Toggle Toggle → → → Chip/sector erase Erase completed Stop Stop →...
Page 595: Data Polling Flag (Dq7)
CHAPTER 28 3M-BIT FLASH MEMORY 28.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated ■ Data Polling Flag (DQ7) Table 28.6-3 lists the data polling flag state transitions (state change for normal operation) and Table 28.6-4 lists the data polling flag state transitions (state change for abnormal operation).
Page 596 CHAPTER 28 3M-BIT FLASH MEMORY ● Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit7 (DATA: 7) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased.
Page 597: Toggle Bit Flag (Dq6)
CHAPTER 28 3M-BIT FLASH MEMORY 28.6.2 Toggle Bit Flag (DQ6) Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle Bit Flag (DQ6) Table 28.6-5 lists the toggle bit flag state transitions (state change for normal operation) and Table 28.6-6 lists the toggle bit flag state transitions (state change for abnormal operation).
Page 598: Timing Limit Exceeded Flag (Dq5)
CHAPTER 28 3M-BIT FLASH MEMORY 28.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Timing Limit Exceeded Flag (DQ5) Table 28.6-7 lists the timing limit exceeded flag state transitions (state change for normal operation) and Table 28.6-8 lists the timing limit exceeded flag state transitions (state change for abnormal operation).
Page 599: Sector Erase Timer Flag (Dq3)
CHAPTER 28 3M-BIT FLASH MEMORY 28.6.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started.
Page 600 CHAPTER 28 3M-BIT FLASH MEMORY ● Read access during sector erase Read-access during execution of sector erase suspend causes the flash memory to output "1" if the address specified by the address signal belongs to the sector being erased. If this address does not belong to the sector being erased, the flash memory outputs bit3 (DATA:3) of the corresponding memory value.
Page 601: Toggle Bit-2 Flag (Dq2)
CHAPTER 28 3M-BIT FLASH MEMORY 28.6.5 Toggle Bit-2 Flag (DQ2) The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the sector is in the erase-suspended state. ■ Toggle Bit-2 Flag (DQ2) Table 28.6-11 lists the toggle bit-2 flag state transitions (state change for normal operation) and Table 28.6- 12 lists the toggle bit-2 flag state transitions (state change for abnormal operation).
Page 602 CHAPTER 28 3M-BIT FLASH MEMORY ● While a sector erase operation is suspended If successive reads are executed while a sector erase operation is suspended, and if the address indicates the sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the sector is not to be erased, the flash memory outputs the read value of the bit2 (DATA: 2) to the location indicated by the address.
Page 603: Detailed Explanation Of Writing To And Erasing Flash Memory
CHAPTER 28 3M-BIT FLASH MEMORY 28.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued. ■...
Page 604: Setting The Read/Reset State
CHAPTER 28 3M-BIT FLASH MEMORY 28.7.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the Flash Memory to the Read/Reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory.
Page 605: Writing Data
CHAPTER 28 3M-BIT FLASH MEMORY 28.7.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory.
Page 606 CHAPTER 28 3M-BIT FLASH MEMORY Figure 28.7-1 Example of the Flash Memory Write Procedure Start writing FMCS: WE (bit 5) Enable flash memory write Write command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XXA0 (4) Write address <-- Write data Read internal address Next address Data...
Page 607: Erasing All Data (Erasing Chips)
CHAPTER 28 3M-BIT FLASH MEMORY 28.7.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. ■ Erasing All Data in the Flash Memory (Erasing Chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory.
Page 608: Erasing Optional Data (Erasing Sectors)
CHAPTER 28 3M-BIT FLASH MEMORY 28.7.4 Erasing Optional Data (Erasing Sectors) This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time. ■...
Page 609 CHAPTER 28 3M-BIT FLASH MEMORY Figure 28.7-2 Example of the Flash Memory Sector Erase Procedure Start erasing FMCS: WE (bit 5) Enable flash memory erase Erase command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA (5) Fx5554 <-- XX55 Sector erase timer (DQ3)
Page 610: Suspending Sector Erase
CHAPTER 28 3M-BIT FLASH MEMORY 28.7.5 Suspending Sector Erase This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased. ■ Suspending Erasing of Flash Memory Sectors Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory.
Page 611: Restarting Sector Erase
CHAPTER 28 3M-BIT FLASH MEMORY 28.7.6 Restarting Sector Erase This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors. ■ Restarting Erasing of Flash Memory Sectors Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command in the command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory.
Page 612: Notes On Using 3M-Bit Flash Memory
CHAPTER 28 3M-BIT FLASH MEMORY 28.8 Notes on using 3M-bit Flash Memory This section contains notes on using 3M-bit flash memory. ■ Notes on Using Flash Memory ● Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum low-level width of 500 ns must be maintained.
Page 613 CHAPTER 28 3M-BIT FLASH MEMORY ● Applying V Applying V required for the sector protect operation should always be started and terminated when the supply voltage is ON.
Page 614: Reset Vector Address In Flash Memory
CHAPTER 28 3M-BIT FLASH MEMORY 28.9 Reset Vector Address in Flash Memory The MB90F394H(A) support a hard-wired reset vector. When the addresses "FFFFDC " to "FFFFDF " are accessed for reading data in internal vector mode, the values that have been determined by the hard-wired logic in advance are read.
Page 615: 28.10 Example Of Programming 3M-Bit Flash Memory
CHAPTER 28 3M-BIT FLASH MEMORY 28.10 Example of Programming 3M-bit Flash Memory This section presents a programming example of 3M-bit flash memory. ■ Programming Example of 3M-bit Flash Memory Flash Memory Sample Program NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------------------- ;3M-bit-Flash test program ;1: Transmits the program (address: FF8000H, sector: SA6) from Flash to RAM (address: 001500H).
Page 616 CHAPTER 28 3M-BIT FLASH MEMORY ;///////////////////////////////////////////////////////////// ;Main program (FFA000H) ;///////////////////////////////////////////////////////////// CODE CSEG START: ///////////////////////////////////////////////////// Initialization ///////////////////////////////////////////////////// CKSCR,#0BAH ;3-multiple setting RP,#0 A,#!STA_T SSB,A MOVW A,#STA_T MOVW SP,A ROMM,#00H ;Mirror OFF PDR0,#00H ;For error check DDR0,#0FFH PDR1,#00H ;Port for data input DDR1,#00H PDR2,#00H ;Port for data output DDR2,#0FFH...
Page 617 CHAPTER 28 3M-BIT FLASH MEMORY ;//////////////////////////////////////////////// ;Write (SA1) ;//////////////////////////////////////////////// A,PDR1 MOVW @RW0+00,A ;PDR1 data allocation to RAM FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H ;Flash write command 3 MOVW A,@RW0+00 ;Input data (RW0) write to flash memory (RW2) MOVW...
Page 618 CHAPTER 28 3M-BIT FLASH MEMORY /////////////////////////////////////// Erase termination check (FMCS-RDY) /////////////////////////////////////// NTOE MOVW A,FMCS A,#10H ;Extraction of FMCS RDY bit (bit 4) ;End of sector erase? FMCS,#00H ;Flash erase mode release RETP ;Return to the main program ;////////////////////////////////////////////// ;Error ;////////////////////////////////////////////// ERROR FMCS,#00H ;Flash mode release...
Page 619: Chapter 29 Examples Of Serial Programming Connection
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION This chapter provides examples of F MC-16LX MB90F394H(A) serial programming connection. 29.1 Basic Configuration of MB90F394H(A) Serial Programming Connection 29.2 Example of Serial Programming Connection 29.3 Example of Serial Programming Connection (Power Supplied From the Programmer) 29.4 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used)
Page 620: Basic Configuration Of Mb90F394H(A) Serial Programming Connection
29.1 Basic Configuration of MB90F394H(A) Serial Programming Connection The MB90F394H(A) supports flash ROM serial onboard programming (Fujitsu standard). This section describes the specifications. ■ Basic Configuration of MB90F394H(A) Serial Programming Connection The AF220/AF210/AF120/AF110 flash microcontroller programmer from Yokogawa Digital Computer Corporation is used for Fujitsu standard serial onboard programming.
Page 621 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION Table 29.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming Function Additional information MD2, MD1 Controls programming mode from the flash microcontroller Mode pins programmer. In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency.
Page 622 AZ221 PC/AT RS232C cable for programmer AZ210 Standard target probe (a) with a 1 m cable FF201 Fujitsu F MC-16LX flash microcontroller control module AZ290 Remote controller 2 MBytes PC card (optional) for flash memory sizes up to 128 KBytes...
Page 623 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION ■ Oscillating Clock Frequency and Serial Clock Input Frequency The equation listed below can be used to calculate the serial clock frequencies that can be used for the MB90F394H(A). Set an appropriate serial clock input frequency in the flash microcontroller programmer according to the oscillating clock frequency in use.
Page 624: Example Of Serial Programming Connection
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 29.2 Example of Serial Programming Connection The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110 ■...
Page 625 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.
Page 626: Example Of Serial Programming Connection (Power Supplied From The Programmer)
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 29.3 Example of Serial Programming Connection (Power Supplied From the Programmer) The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110 ■...
Page 627 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.
Page 628: Example Of Minimum Connection To The Flash Microcontroller Programmer (User Power Supply Used)
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 29.4 Example of Minimum Connection to the Flash Microcontroller Programmer (User Power Supply Used) Figure 29.4-1 shows the example of minimum connection to the flash microcontroller programmer (user power supply used). Serial reprogramming mode: MD2, MD1, MD0 = 110 ■...
Page 629 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.
Page 630: Example Of Minimum Connection To The Flash Microcontroller Programmer (Power Supplied From The Programmer)
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 29.5 Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied From the Programmer) Figure 29.5-1 shows the example of minimum connection to the flash microcontroller programmer (power supplied from the programmer). Serial reprogramming mode: MD2, MD1, MD0 = 110 ■...
Page 631 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION • Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.
Page 632 CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION...
Page 633: Appendix
APPENDIX The appendixes provide I/O maps, instructions, and other information. APPENDIX A I/O Maps APPENDIX B Instructions APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX D List of Interrupt Vectors...
Page 634: Appendix A I/O Maps
APPENDIX APPENDIX A I/O Maps Table A-1 lists addresses to be assigned to the registers in the peripheral blocks. ■ I/O Maps Table A-1 I/O Map (1/6) Address Register Abbreviation Access Peripheral Initial value 000000 XXXXXXXX Port 0 data register PDR0 Port 0 000001...
Page 635 APPENDIX A I/O Maps Table A-1 I/O Map (2/6) Address Register Abbreviation Access Peripheral Initial value 000017 00000000 Port 7 direction register DDR7 Port 7 000018 00000000 Port 8 direction register DDR8 Port 8 000019 00000000 Port 9 direction register DDR9 Port 9 00001A...
Page 636 APPENDIX Table A-1 I/O Map (3/6) Address Register Abbreviation Access Peripheral Initial value 000034 00000000 A/D Control Status 0 ADCS0 000035 00000000 A/D Control Status 1 ADCS1 A/D Converter 000036 XXXXXXXX A/D Data 0 ADCR0 000037 00000XXX A/D Data 1 ADCR1 PPG0 operation mode control 000038...
Page 637 APPENDIX A I/O Maps Table A-1 I/O Map (4/6) Address Register Abbreviation Access Peripheral Initial value PPG8 operation mode control 000048 0X000XX1 PPGC8 register PPG9 operation mode control 16-bit Programable 000049 0X000001 PPGC9 register Pulse Generator 8/9 PPG8 and PPG9 clock select 00004A 000000XX PPG89...
Page 638 APPENDIX Table A-1 I/O Map (5/6) Address Register Abbreviation Access Peripheral Initial value 000060 000XX000 Watch Timer Control WTCR Watch Timer 000061 00000000 Watch Timer Control WTCR Stepping Motor 000062 00000XX0 PWM Control 0 PWC0 Controller 0 000063 Reserved Stepping Motor 000064 00000XX0 PWM Control 1...
Page 639 APPENDIX A I/O Maps Table A-1 I/O Map (6/6) Address Register Abbreviation Access Peripheral Initial value 0000A2 Reserved 0000A7 0000A8 XXXXX111 Watchdog Control WDTC Watchdog Timer 0000A9 1XX00100 Time-Base Timer Control TBTC Time-Base Timer 0000AA Reserved 0000AD Flash Control Status 0000AE 000X0000 (Flash devices only.
Page 640 APPENDIX ■ I/O Map (35XX Addresses) Table A-2 I/O Map (35XX Addresses) (1/8) Address Register Abbreviation Access Peripheral Initial value 003500 XXXXXXXX Reload L PRLL0 003501 XXXXXXXX Reload H PRLH0 16-bit Programable Pulse Generator 0/1 003502 XXXXXXXX Reload L PRLL1 003503 XXXXXXXX Reload H...
Page 641 APPENDIX A I/O Maps Table A-2 I/O Map (35XX Addresses) (2/8) Address Register Abbreviation Access Peripheral Initial value 003518 00000000 Serial Mode Register SMR3 003519 00000000 Serial Control Register SCR3 00000000 Reception/Transmission Data 00351A RDR3/TDR3 Register 11111111 00351B 00001000 Serial Status Register SSR3 Extended Communication UART3...
Page 642 APPENDIX Table A-2 I/O Map (35XX Addresses) (3/8) Address Register Abbreviation Access Peripheral Initial value 003530 XXXXXXXX Output Compare 0 OCCP0 003531 XXXXXXXX Output Compare 0 OCCP0 Output Compare 0/1 003532 XXXXXXXX Output Compare 1 OCCP1 003533 XXXXXXXX Output Compare 1 OCCP1 003534 XXXXXXXX...
Page 643 APPENDIX A I/O Maps Table A-2 I/O Map (35XX Addresses) (4/8) Address Register Abbreviation Access Peripheral Initial value 00354A XXXXXXXX Sub-second Data WTBR(0) 00354B XXXXXXXX Sub-second Data WTBR(0) 00354C XXXXXXXX Sub-second Data WTBR(1) Watch Timer 00354D XXXXXXXX Second Data WTSR 00354E XXXXXXXX Minute Data...
Page 644 APPENDIX Table A-2 I/O Map (35XX Addresses) (5/8) Address Register Abbreviation Access Peripheral Initial value 003564 XXXXXXXX PWM1 Compare 5 PWC15 003565 XXXXXXXX PWM2 Compare 5 PWC25 Stepping Motor Controller 5 003566 XX000000 PWM1 Select 5 PWS15 003567 X0000000 PWM2 Select 5 PWS25 Output Compare Control 003568...
Page 645 APPENDIX A I/O Maps Table A-2 I/O Map (35XX Addresses) (6/8) Address Register Abbreviation Access Peripheral Initial value 0035AB 00011111 ICCR C clock control register C Interface 0035AC Reserved 0035AF 0035B0 Reserved 0035BF 0035C0 11111101 Parameter Register Low Byte CMPRL 0035C1 XX000010 Parameter Register High Byte...
Page 646 APPENDIX Table A-2 I/O Map (35XX Addresses) (7/8) Address Register Abbreviation Access Peripheral Initial value Program Address Detection 0035E0 XXXXXXXX PADR0 Register 0 Program Address Detection 0035E1 XXXXXXXX PADR0 Register 0 Program Address Detection 0035E2 XXXXXXXX PADR0 Register 0 Address Match Detection 0 Program Address Detection 0035E3...
Page 647 APPENDIX A I/O Maps Table A-2 I/O Map (35XX Addresses) (8/8) Address Register Abbreviation Access Peripheral Initial value 003800 Reserved for CAN Interface 1. Refer to section about CAN Controller 0038FF 003900 Reserved for CAN Interface 1. Refer to section about CAN Controller 0039FF 003A00 Reserved for CAN Interface 2.
Page 648 APPENDIX • "X" indicates an undefined value. • Any write access to reserved addresses in I/O map should not be performed. A read access to reserved address results in reading "X". ● Explanation of write and read R/W: Both read and write enabled Only read enabled Only write enabled ●...
Page 649: Appendix B Instructions
APPENDIX B Instructions APPENDIX B Instructions APPENDIX B describes the instructions used by the F MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map Code: CM44-00202-1E...
Page 650: Instruction Types
APPENDIX Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 651: Addressing
APPENDIX B Instructions Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 652 APPENDIX ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to the (RL1) byte, word, and long word types in order from the None left.
Page 653: Direct Addressing
APPENDIX B Instructions Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2 2 3 3...
Page 654 APPENDIX Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general- purpose register R0.) Before execution A 0 7 1 6 2 5 3 4 Memory space After execution A 0 7 1 6 2 5 6 4 Memory space...
Page 655 APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.)
Page 656 APPENDIX ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
Page 657 APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 to 0000FF explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Page 658 APPENDIX ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.)
Page 659: Indirect Addressing
APPENDIX B Instructions Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 660 APPENDIX Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0 7 1 6 2 5 3 4 Memory space RW1 D 3 0 F...
Page 661 APPENDIX B Instructions ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.)
Page 662 APPENDIX ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general- purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.)
Page 663 APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
Page 664 APPENDIX Figure B.4-9 Example of Register List (rlist) POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E × × × × 0 2 0 1 ×...
Page 665 APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB).
Page 666 APPENDIX ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3 C 2 0...
Page 667: Execution Cycle Count
APPENDIX B Instructions Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■...
Page 668 APPENDIX ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode Register access count in Code Operand each addressing mode Execution cycle count in each addressing mode See the instruction list.
Page 669 APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address...
Page 670: Effective Address Field
APPENDIX Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Byte count of extended Code Representation Address format address part (RL0) Register direct: Individual parts correspond to (RL1) the byte, word, and long word types in order from the left.
Page 671: How To Read The Instruction List
APPENDIX B Instructions How to Read the Instruction List Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Description Uppercase, symbol: Represented as is in the assembler.
Page 672 APPENDIX Table B.7-1 Description of Items in the Instruction List (1/2) Item Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change S: Set upon instruction execution.
Page 673 APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol Explanation R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Abbreviated direct addressing addr16 Direct addressing addr24...
Page 674: F 2 Mc-16Lx Instruction List
APPENDIX MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F MC-16LX. ■ F MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic Operation byte (A) ← (dir) A,dir byte (A) ← (addr16) A,addr16 byte (A) ←...
Page 675 APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic Operation word (A) ← (dir) MOVW A,dir word (A) ← (addr16) MOVW A,addr16 word (A) ← (SP) MOVW A,SP word (A) ← (RWi) MOVW A,RWi word (A) ← (ear) MOVW A,ear word (A) ←...
Page 676 APPENDIX Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← (A) + imm8 A,#imm8 byte (A) ← (A) + (dir) A,dir byte (A) ← (A) + (ear) A,ear byte (A) ← (A) + (eam) A,eam 4 + (a) byte (ear) ←...
Page 677 APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic Operation byte (ear) ← (ear) + 1 2 × (b) byte (eam) ← (eam) + 1 5+(a) byte (ear) ← (ear) - 1 2 × (b) byte (eam) ← (eam) - 1 5+(a) word (ear) ←...
Page 678 APPENDIX Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) DIVU A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) DIVU A,eam word (A) / byte (eam)
Page 679 APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) A,eam word (A) / byte (eam) quotient →...
Page 680 APPENDIX Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic Operation byte (A) ← (A) and imm8 A,#imm8 byte (A) ← (A) and (ear) A,ear byte (A) ← (A) and (eam) A,eam 4+(a) byte (ear) ← (ear) and (A) ear,A 2 ×...
Page 681 APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic Operation long (A) ← (A) and (ear) ANDL A,ear long (A) ← (A) and (eam) ANDL A,eam 7+(a) long (A) ← (A) or (ear) A,ear long (A) ← (A) or (eam) A,eam 7+(a) long (A) ←...
Page 682 APPENDIX Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← Right rotation with carry RORC byte (A) ← Right rotation with carry ROLC byte (ear) ← Right rotation with carry RORC 2 × (b) byte (eam) ← Right rotation with carry RORC 5+(a) byte (ear) ←...
Page 683 APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/ Branch on (Z) = 0 BC/BLO rel Branch on (C) = 1 BNC/ Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0...
Page 684 APPENDIX Table B.8-14 19 Branch 2 Instructions Mnemonic Operation S T N Z V C CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8 CBNE eam,#imm8,rel *9 Branch on byte (eam) not equal to imm8...
Page 685 APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic Operation word (SP) ← (SP) - 2, ((SP)) ← (A) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (AH) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (PS) PUSHW (SP) ←...
Page 686 APPENDIX Table B.8-16 21 Bit Operand Instructions Mnemonic Operation byte (A) ← (dir:bp)b MOVB A,dir:bp byte (A) ← (addr16:bp)b MOVB A,addr16:bp byte (A) ← (io:bp)b MOVB A,io:bp 2 × (b) bit (dir:bp)b ← (A) MOVB dir:bp,A 2 × (b) bit (addr16:bp)b ← (A) MOVB addr16:bp,A 2 ×...
Page 687 APPENDIX B Instructions Table B.8-18 10 String Instructions Mnemonic Operation byte transfer @AH+ ← @AL+, counter = RW0 MOVS / MOVSI byte transfer @AH- ← @AL-, counter = RW0 MOVSD byte search @AH+ ← AL, counter = RW0 SCEQ / SCEQI byte search @AH- ←...
Page 688: Instruction Map
APPENDIX Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map : Byte 1 Character string...
Page 689 APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction . . . Byte 1 Byte 2 Operand Operand code [Basic page map] [Extended page map]* *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
Page 690 APPENDIX Table B.9-2 Basic Page Map...
Page 691 APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (First Byte = 6C...
Page 692 APPENDIX Table B.9-4 Character String Operation Instruction Map (First Byte = 6E...
Page 693 APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (First Byte = 6F...
Page 694 APPENDIX Table B.9-6 ea Instruction 1 (First Byte = 70...
Page 695 APPENDIX B Instructions Table B.9-7 ea Instruction 2 (First Byte = 71...
Page 696 APPENDIX Table B.9-8 ea Instruction 3 (First Byte = 72...
Page 697 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (First Byte = 73...
Page 698 APPENDIX Table B.9-10 ea Instruction 5 (First Byte = 74...
Page 699 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (First Byte = 75...
Page 700 APPENDIX Table B.9-12 ea Instruction 7 (First Byte = 76...
Page 701 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (First Byte = 77...
Page 702 APPENDIX Table B.9-14 ea Instruction 9 (First Byte = 78...
Page 703 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79...
Page 704 APPENDIX Table B.9-16 MOV Ri, ea Instruction (First Byte = 7A...
Page 705 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7B...
Page 706 APPENDIX Table B.9-18 MOV ea, Ri Instruction (First Byte = 7C...
Page 707 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7D...
Page 708 APPENDIX Table B.9-20 XCH Ri, ea Instruction (First Byte = 7E...
Page 709 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7F...
Page 710: Appendix C Timing Diagrams In Flash Memory Mode
APPENDIX APPENDIX C Timing Diagrams in Flash Memory Mode Each timing diagram for the external pins of the Flash devices in MB90390 series during Flash Memory mode is shown below. ■ Data Read by Read Access Figure C-1 Timing Diagram for Read access...
Page 711 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Write, Data Polling, Read (WE Control) Figure C-2 Write, Data Polling, Read (WE Control) Third bus cycle Data polling AQ18 7AAAA GHWL WHWH1 5.0 V Write address Write data DQ7: Reverse output of write data : Output of write data Note: The last two bus cycle sequences out of the four are described.
Page 712 APPENDIX ■ Write, Data Polling, Read (CE Control) Figure C-3 Timing Diagram for Write access (CE Control) Third bus cycle Data polling 7AAAA AQ18 to AQ0 GHWL WHWH1 DQ7 to DQ0 5.0 V PA: Write address PD: Write data DQ7: Reverse output of write data : Output of write data Note: The last two bus cycle sequences out of the four are described.
Page 713 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Chip Erase/Sector Erase Command Sequence Figure C-4 Timing Diagram for Write access (Chip Erasing/sector Erasing) AQ18 7AAAA 75555 7AAAA 7AAAA 75555 GHWL Note: SA is the sector address at sector erasing. 7AAAA (or 6AAAA ) is the address at chip erasing.
Page 714 APPENDIX ■ Data Polling Figure C-5 Timing Diagram for Data Polling High impedance DQ7 = Valid data WHWH1 WHWH2 DQ6toDQ0 DQ6 to DQ0 DQ6 to DQ0 = Invalid = Valid data Note: DQ7 is valid data (The device terminates automatic operation). ■...
Page 715 APPENDIX C Timing Diagrams in Flash Memory Mode Note: DQ6 stops toggling (The device terminates automatic operation). ■ RY/BY Timing During Writing/Erasing Figure C-7 Timing Diagram for Output of RY/BY Signal During Writing/Erasing Rising edge of last write pulse Writing or erasing RY/BY BUSY ■...
Page 716 APPENDIX ■ Enable Sector Protect/Verify Sector Protect Figure C-9 Enable Sector Protect/Verify Sector Protect AQ18 to AQ9 AQ8, AQ2, and AQ1 (AQ8, AQ2, AQ1) = (0, 1, 0) 12 V 12 V VLHT VLHT OESP DQ7 to DQ0 : First sector address : Next sector address...
Page 717 APPENDIX C Timing Diagrams in Flash Memory Mode ■ Temporary Sector Protect Cancellation Figure C-10 Temporary Sector Protect Cancellation 12 V Write/erase command sequence VLHT RY/BY...
Page 718 The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00 to FFFFFF in the memory area and also used for software interrupts. ■ List of Interrupt Vectors Table D-1 lists the interrupt vectors for the MB90390 series. Table D-1 Interrupt Vectors (1/2) Software Vector Vector...
Page 719 APPENDIX D List of Interrupt Vectors Table D-1 Interrupt Vectors (2/2) Software Vector Vector Vector Mode Interrupt interrupt Hardware interrupt address L address M address H register instruction FFFFA0 FFFFA1 FFFFA2 INT 23 Unused 16-bit reload timer 0 FFFF9C FFFF9D FFFF9E INT 24 Unused...
Page 720 ■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control registers of the MB90390 series. Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1/2) Interrupt vector...
Page 721 APPENDIX D List of Interrupt Vectors Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2) Interrupt vector Interrupt control register Interrupt cause clear Number Address Number Address FFFF78 Serial I/O 0000BB ICR11 FFFF74 Sound generator FFFF70 UART0 RX 0000BC ICR12 FFFF6C...
Page 722 APPENDIX...
Page 723 INDEX The index follows on the next page. This is listed in alphabetic order.
Page 724 Index Numerics Sector Configuration of the 3M-bit Flash Memory ..........558 16-bit Free-run Timer 8/10-bit A/D Converter 16-bit Free-run Timer ........192 8/10-bit A/D Converter Interrupts...... 294 16-bit Free-run Timer 0 and 1......194 8/10-bit A/D Converter Interrupts and 16-bit Free-run Timer Block Diagram ....196 OS ..........
Page 725 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)......493 Accumulator (A)..........39 AMSR A/D Control Status Register Acceptance Mask Select Register (AMSR) ..491 A/D Control Status Register 0 (ADCS0) .... 290 Analog Input Enable Register Upper Bits of the A/D Control Status Register 1 Analog Input Enable Registers ....175, 285 (ADCS1)..........
Page 726 CAN Controller Block Diagram of MB90394HA/MB90F394H(A) ....8 Block Diagram of CAN Controller ....457 Block Diagram of MB90V390H ......6 Canceling a Transmission Request from the CAN Block Diagram of Controller........... 501 MB90V390HA/MB90V390HB ....7 Features of CAN Controller ......456 Block Diagram of ROM Mirroring Module..
Page 727 Registers of Clock Modulator......108 CPU Operating Modes CPU Operating Modes and Current Clock Modulator Control Register Consumption........138 Clock Modulator Control Register (CMCR) ..109 Clock Output Enable Register Control Status Register (CSR) (Lower)....467 Clock Output Enable Register ......103 Current Consumption Clock Selection Register CPU Operating Modes and Current...
Page 728 DIRR OS Function of the 8/10-bit A/D Delayed Interrupt Cause Issuance/Cancellation Converter ........... 294 Register (DIRR: Delayed Interrupt Request OS Operation Flow ........77 Register)..........83 OS Status Register (ISCS)......75 Extended Intelligent I/O Service (EI OS) ..55, 71 DIV A, Ri Intelligent I/O Service (EI OS) Function and...
Page 729 Extended Status/Control Register Writing Data to the Flash Memory .....577 Extended Status/Control Register Writing to the Flash Memory ......577 (ESCR2/ESCR3)......... 359 Writing to/Erasing Flash Memory ......556 External Clock Flash Memory Control Status Register Connection of an Oscillator or an External Clock to the Flash Memory Control Status Register Microcontroller........
Page 730 Hardware Sequence Flags Indirect Addressing Hardware Sequence Flags ......... 565 Indirect Addressing .......... 631 Input Capture Input Capture........... 215 Input Capture (2 Channels per One Module)..193 I/O Area Input Capture Block Diagram......215 I/O Area ............28 Sample of Input Capture Fetch Timing....221 I/O Maps Input Capture Data Register I/O Maps ............
Page 731 LIN-UART Release of the Standby Mode by an Interrupt ........159 LIN-UART2, UART3 Interrupts ......365 Switching to a Standby Mode and Interrupt ..159 LIN-UART2, UART3 Interrupts and EI OS..367 Interrupt Control Register Low-power Consumption Interrupt Causes,Interrupt Vectors,and Interrupt Block Diagram of the Low-power Consumption Control Registers ........
Page 732 Modulation Parameter Register For -H Devices,e.q. MB90F394H and MB90V390H: Caution for Disabling Message Buffers by Modulation Parameter Register ......114 BVAL Bits ......... 519 Modulation Parameter Register Contents.... 115 Pin Assignment of MB90V390H ......9 Multi-byte Data MB90V390HA Accessing Multi-byte Data........35 Pin Assignment of Multi-byte Data Allocation MB90V390HA/MB90V390HB ....
Page 733 Output Compare ..........203 PPG0 Operation Mode Control Register Output Compare PPG0 Operation Mode Control Register (2 Channels per One Module)....192 (PPGC0) ..........255 Output Compare Register........204 PPG0/1 Clock Select Register Output Compare Timing PPG0/1 Clock Select Register (PPG01) ....259 Output Compare Timing ........
Page 734 Reception Data Register Notes on Changing the PWM Setting Reception Data Register (RDR2/RDR3)..... 357 Values..........531 Reception Flowchart PWM Control 0 Register Reception Flowchart of the CAN Controller ..507 PWM Control 0 Register........524 Reception Interrupt PWM1 and PWM2 Compare Registers Reception Interrupt Generation and Flag Set PWM1 and PWM2 Compare Registers....
Page 735 RFWTR Serial Control Register Remote Frame Receiving Wait Register Serial Control Register (SCR2/SCR3) ....350 (RFWTR)........... 483 Serial I/O RIER Interrupt Function of the Extended Serial I/O Reception Interrupt Enable Register (RIER) ..490 Interface ..........453 Serial I/O Block Diagram ........438 ROM Mirroring Module Serial I/O Operation........446, 448 Block Diagram of ROM Mirroring Module ..
Page 736 Status of Pins during a Reset ......136 Watchdog Timer Behavior in Stop Mode, Time-base Timer Mode, and Sleep Mode....188 Status Register Status Register (USR) ........317 Priorities of the STP,SLP,and TMD Bits..... 146 Stepping Motor Controller SMCS Block Diagram of Stepping Motor Upper Byte of Serial Mode Control Status Register Controller...........
Page 737 Ten Bit Slave Address Register Transmission Ten Bit Slave Address Register (ITBA) ..... 422 Procedure for Transmission by Message Ten Bit Slave Address Register (ITBA) Buffer (x)..........510 Contents..........422 Transmission Cancel Register TIER Transmission Cancel Register (TCANR) ....484 Transmission Interrupt Enable Register Transmission Complete Register (TIER) ..........
Page 738 Undefined Instruction Exception Due to Execution of an Undefined Watch Timer Instruction ..........80 Block Diagram of Watch Timer ......238 Execution of an Undefined Instruction ....80 Watch Timer Registers Underflow Operation Watch Timer Registers ........239 Underflow Operation of 16-bit Reload Watchdog Timer ..........
Page 739 CM44-10122-4E FUJITSU MICROELECTRONICS • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90390 Series HARDWARE MANUAL July 2008 the fourth edition FUJITSU MICROELECTRONICS LIMITED Published Edited Business & Media Promotion Dept.

Fujitsu MB90390 Series Hardware Manual

Chapter 1 Overview

Chapter 2 Cpu

Chapter 3 Interrupts

Chapter 4 Delayed Interrupt

Chapter 5 Clocks

Chapter 6 Clock Modulator

Chapter 7 Resets

Chapter 8 Low-Power Control Circuit

Chapter 9 Memory Access Modes

Chapter 10 I/O Ports

Chapter 11 Time-Base Timer

Chapter 12 Watchdog Timer

Chapter 13 16-Bit I/O Timer

Chapter 14 16-Bit Reload Timer (with Event Count Function)

Chapter 15 Watch Timer

Chapter 16 8/16-Bit Ppg

Chapter 17 Dtp/External Interrupts

Chapter 18 8/10-Bit A/D Converter

Chapter 19 Uart0, Uart1

Chapter 20 Uart2, Uart3

CHAPTER 21 400 Khz I 2 C INTERFACE

Chapter 22 Serial I/O

Chapter 23 Can Controller

Chapter 24 Stepping Motor Controller

Chapter 25 Sound Generator

Chapter 26 Address Match Detection Function

Chapter 27 Rom Mirroring Module

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Summary of Contents for Fujitsu MB90390 Series