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CHAPTER 3 CPU AND CONTROL UNITS
[bit1] OSCD2 (OSCillation Disable mode for XIN2)
This bit controls stopping of the sub-oscillation input (XIN2) in stop mode.
0
1
•
This bit is initialized to 1 by a reset (INIT).
•
This bit is readable and writable.
[bit0] OSCD1 (OSCillation Disable mode for XIN1)
This bit controls stopping of main oscillation input (XIN1) in stop mode.
0
1
•
This bit is initialized to 1 by a reset (INIT).
•
This bit is readable and writable.
■ Time Base Counter Control Register (TBCR)
Figure 3.11-4 shows the configuration of the time base counter control register (TBCR) bits.
Figure 3.11-4 Configuration of Time Base Counter Control Register (TBCR) Bits
Address: 00000482
Initial value (INIT)
Initial value (RST)
The time base counter control register controls time base timer interrupts, among other things.
This register enables time base timer interrupts, selects an interrupt interval time, and sets an
optional function for the reset operation.
[bit15] TBIF (TimeBasetimer Interrupt Flag)
This bit is the time base timer interrupt flag. It indicates that the interval time (TBC2-0 bits,
which are bit13 to bit11) specified by the time base counter has elapsed.
A time base timer interrupt request is generated if this bit is set to 1 when interrupts are
enabled by bit14 (TBIE bit, TBIE=1).
Clear source
Set source
•
This bit is initialized to 0 by a reset (RST).
•
This bit is readable and writable, although only 0 can be written to it. Writing 1 does not
change the bit value. The value read by a read modify write instruction is always 1.
88
Not stopping the sub-oscillation in stop mode
Stopping the sub-oscillation in stop mode (initial value)
Main oscillation does not stop in stop mode.
Main oscillation stops in stop mode (initial value).
bit
15
14
TBIF
TBIE TBC2 TBC1 TBC0
H
0
0
0
0
R/W
R/W
An instruction writes 0.
The specified interval time elapses (the trailing edge of the time base
counter is detected).
13
12
11
10
-
x
x
x
x
x
x
x
x
R/W
R/W
R/W R/W
9
8
SYNCR SYNCS
0
0
x
x
R/W
R/W
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