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CHAPTER 17 USB FUNCTION
■ Example of Controlling DMA Reception
Figure 17.3-13 shows an example of controlling DMA reception.
Clear the FIFOBUSY1 bit of
CONT4 (control register) to 0
Set the DFIFOBUSY1 bit of
CONT5 (control register) to 1
Set the MDREQ1 bit of CONT6
(control register) to 1
432
Figure 17.3-13 Example of Controlling DMA Reception
Start of reception operation
Write total receive byte
count to TRSIZE
(control register)
Set the TRCNTEN bit of
CONT10 (control register)
to 1
Is DREQ asserted?
YES
Read receive data
(2 bytes) from FIFO
buffer for reception
Is IRQ asserted?
YES
Read the TRCVEND bit
of ST5 (status register)(*1)
End of reception operation
To use the total receive byte counter,
perform these operations before reading
data from the FIFO buffer.
NO
NO
*:
No interrupts occur if the total receive
byte counter is not used.
The end of total data transfer must
be determined by a method other
than the macro program.
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