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CHAPTER 3 CPU AND CONTROL UNITS
■ PLL Multiply-by Rate
Set the multiply-by rate of the main PLL in bit14 to bit12 (PLL1S2, PLL1S1, and PLL1S0 bits) of
the clock source control register (CLKR).
After a setting initialization reset (INIT), all bits are initialized to 0.
❍ PLL multiply-by rate setting
To change the PLL multiply-by rate setting from the initial value, do so before or as soon as the
PLL is enabled after the program has started execution. After changing the multiply-by rate,
switch the source clock after the lock wait time elapses. For the PLL lock wait time, use of a time
base timer interrupt is recommended.
To change the PLL multiply-by rate setting during operation, switch the source clock to a clock
other than the PLL in question before making the change. After changing the multiply-by rate,
switch the source clock after the lock wait time has elapsed, as described above.
You can also change the PLL multiply-by rate setting while using a PLL. In this case, however,
the program stops running after the device automatically enters the oscillation stabilization wait
state after the multiply-by rate setting is rewritten and does not resume execution until the
specified oscillation stabilization wait time has elapsed.
The program does not stop running if the clock source is switched to a clock other than a PLL.
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