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CHAPTER 5 16-BIT RELOAD TIMER
5.2.1
Control Status Register (TMCSR)
The control status register (TMCSR) controls the operating modes and interrupts of the
16-bit timer.
■ Bit Configuration of the Control Status Register (TMCSR)
Figure 5.2-2 Bit Configuration of the Control Status Register (TMCSR)
TMCSR
bit
Address:
11
0000004E
H
00000056
CSL1 CSL0 MOD2 MOD1 MOD0 "0"
H
0000005E
H
R/W R/W R/W R/W R/W
Rewrite bits other than the UF, CNTE, and TRG bits only when CNTE=0.
The control status register (TMCSR) supports simultaneous writing.
■ Bit Functions of the Control Status Register (TMCSR)
The following describes the bit functions of the control status register (TMCSR).
[bit11, bit10] CSL1, CSL0 (Count clock SLect)
These bits are the count clock select bits. Table 5.2-1 shows the clock sources that can be
selected using these bits. Countable edges used when external event count mode are set
using the MOD1 and MOD0 bits.
Table 5.2-1 Clock Sources Set Using the CSL Bits
CSL1
0
0
1
1
Note: The minimum pulse width required for an external clock is 2T (T: Peripheral clock
machine cycle).
140
10
9
8
7
CSL0
0
1
0
1
6
5
4
3
OUTL RELD INTE
R
R/W R/W
R/W
Clock source (φ: Machine clock)
External clock (event)
2
1
0
Initial value
000000
UF CNTE TRG
000000
R/W R/W R/W
1
φ/2
3
φ/2
5
φ/2
B
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