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APPENDIX E Macro Reset
This section describes the macro reset register for controlling the USB function and the
OSDC reset.
CS2X area
0x0006FFFE
•
USB-F-RST
Reset signal for USB function. Writing 1 to this bit resets the signal, and writing 0 clears the
signal.
•
OSD-RST
Reset signal for the OSDC. Writing 1 to this bit resets the signal, and writing 0 clears the
signal.
Note:
When the OSDC is set the corresponding reset bit to 1, the register access is performed. Therefore,
the CPU is stopped (the external interface is used the RDY enabled) because the response is not
returned.
Also, the CPU is stopped when the clock is not supplied to the OSDC.
Accessing to the OSDC is used as follow.
• The state which the corresponding reset bit is cleared 0.
• The state which the corresponding clock is supplied.
Figure E-1 Macro Reset Register
7
6
5
USB-F-
H
RST
-
0
-
4
3
2
OSD-
RST
-
0
-
APPENDIX E Macro Reset
1
0
-
-
Initial value
691
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