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Simultaneous Occurrence of a DMA Transfer Request and
an External Hold Request
DMA Transmission
Example of Controlling DMA Transmission
DMAC
AC Characteristics of DMAC
DMA Controller (DMAC) Registers
DMAC (DMA Controller)
DMAC Interrupt Control
DMACA
Control/Status Registers A (DMACA0 to 4)
DMACB
Control/Status Register B (DMACB0 to 4)
DMACR
All-Channel Control Register (DMACR)
DMADA
Transfer Source/Transfer Destination Address Setting
Registers (DMASA0 to 4/DMADA0 to 4)
.......................................................... 336
DMASA
Transfer Source/Transfer Destination Address Setting
Registers (DMASA0 to 4/DMADA0 to 4)
.......................................................... 336
Dot Clock
......................................................... 689
Dot Clock
External Dot Clock Input
Input Dot Clock Selection Control
Internal VCO Generation Dot Clock Input
Output Dot Clock Control
Dot Clock Generation
Dot Clock Generation PLL
Double Buffer
.................................................... 436
Double Buffer
DREQ
Minimum Effective Pulse Width of the DREQ Pin Input
.......................................................... 365
Pin Function of the DACK, and DEOP, and DREQ Pins
.......................................................... 340
Timing of the DREQ Pin Input for Continuing Transfer Over
the Same Channel
Timing to Stop a Demand Transfer Request and Timing to
Invalidate the DREQ Pin Input
DSTP
Timing of the DSTP Pin Input
E
EIRR
External Interrupt Source Register (EIRR)
EIT
EIT (Exception, Interrupt, and Trap)
.......................................................... 49
EIT Causes
.................................................... 60
EIT Operations
.................................................. 54
EIT Vector Table
Priority of EIT Causes To Be Accepted
................................................... 49
Return from EIT
........................ 357
............. 433
................................ 369
....................... 322
........................................ 3
...................................... 362
............. 324
............... 329
................. 338
...................................... 543
.......................... 543
................ 544
..................................... 547
................................... 688
.................................. 368
................. 365
............................... 368
................ 221
......................... 49
..................... 58
ELVR
External Interrupt Request Level Setting Register (ELVR)
..........................................................222
End Point Buffer
Setting of End Point Buffer
ENIR
Interrupt Enable Register (ENIR)
Enter Timer Control Register
Enter Timer Control Register (TxR)
Erase
.............................................661
Sector Erase Restart
Temporary Sector Erase Stop
.....................................................653
Writing/Erase
Erasure
Data Erasure (Chip Erasure)
....................................................658
Sector Erasure
Error
..........................................................313
Bus Error
Communication Error that Causes No Error
..........................................63
Coprocessor Error Trap
Stopping Due To an Error
Event Count Mode
.......................................182, 185
Event Count Mode
Exception
EIT (Exception, Interrupt, and Trap)
Extended Display
Character Background Extended Display
(Setting for Each Line)
External Bus Clock
External Bus Clock (CLKT)
External Bus Interface
External Bus Interface Setting
External Dot Clock
External Dot Clock Input
External Event Count Operation
External Event Count Operation
External Hold
DMA Transfer Request during External Hold
External Hold Request During DMA Transfer
Simultaneous Occurrence of a DMA Transfer Request and
an External Hold Request
External I/O
Transfer Between External I/O and External Memory
..........................................................369
External Interrupt
Block Diagram of the External Interrupt and NMI Controller
..........................................................218
External Interrupt Request Level
Operating Procedure for an External Interrupt
Operation of an External Interrupt
External Interrupt and NMI Controller
External Interrupt and NMI Controller Registers
External Interrupt Request Level Setting Register
External Interrupt Request Level Setting Register (ELVR)
..........................................................222
External Interrupt Source Register
External Interrupt Source Register (EIRR)
....................................424
............................220
........................178
.................................660
..................................657
...............313
.....................................360
..........................49
............................521
....................................81
................................693
......................................543
.............................148
............357
............357
.........................357
.............................224
............223
...........................223
.........219
................221
729
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