Operation Of The External Interrupt And Nmi Controller - Fujitsu MB91319 Series Hardware Manual

10.3

Operation of the External Interrupt and NMI Controller

If, after a request level and an enable register are defined, a request defined in the ELVR
register is input to the corresponding pin, this module generates an interrupt request
signal to the interrupt controller.
■ Operation of an External Interrupt
For simultaneous interrupt requests from resources, the interrupt controller determines the
interrupt request with the highest priority and generates an interrupt for it.
Figure 10.3-1 shows external interrupt operation.
External interrupt
ELVR
EIRR
ENIR
Source
■ Return from Standby
To use an external interrupt to return from the standby state in the clock stop mode, use a level
request as the input request.
If you use an edge request, the device does not return from the stop state in clock stop mode.
■ Operating Procedure for an External Interrupt
Set up a register located inside the external interrupt controller as follows:
1. Disable the target bit in the enable register.
2. Set the target bit in the request level setting register.
3. Clear the target bit in the interrupt source register.
4. Enable the target bit in the enable register.
Simultaneous writing of 16-bit data is supported for steps "3." and "4.".
Before setting a register in this module, you must disable the enable register. In addition, before
enabling the enable register, you must clear the interrupt source register. This procedure is
required to prevent an interrupt source from occurring by mistake while a register is being set or
an interrupt is enabled.
CHAPTER 10 EXTERNAL INTERRUPT AND NMI CONTROLLER
Figure 10.3-1 External Interrupt Operation
Resource
Interrupt controller
request
ICR y y
ICR x x
IL
CMP
ILM
CPU
CMP
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