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■ Bus Error
A bus error is recognized and the I
•
A violation of the basic convention on the I
is detected.
•
A stop condition in master mode is detected.
•
A violation of the basic convention on the I
Note:
The bus error of a 10-bit mode addressing is detected when a 10-bit address is disabled.
■ Communication Error that Causes No Error
If an incorrect clock is generated on the SCL line due to noise or some other reason during
transmission in master mode, the transmission bit counter of the I
causing the slave to hang while the L level appears on the SDA line in the ACK cycle. An error
(AL = 1, BER = 1) does not occur for such an incorrect clock.
If this situation occurs, perform the following error processing:
1. Determine that when MSS = 1, TRX = 1, INT = 1, and LRB = 1, there is a communication
error.
2. Set EN to 0, and then set EN to 1 to cause SCL to generate one clock on a pseudo basis.
This action causes the slave to release the bus.
The period from when EN is set to 0 until EN is set to 1 must be long enough for the slave to
recognize it as a clock (about as long as the H period of a transmission clock).
3. Since IBSR and IBCR are cleared when EN is set to 0, perform retransmission processing
from the START condition. At this time, a STOP condition cannot be generated even if BSS is
set to 0.
Insert an interval equal to or longer than n × 7 × t
and the point where MSS is set to 1 (START condition).
Example:
High-speed mode: 6 × 7 × 30.3 ≅ about 1.273 ms
Standard mode: 27 × 7 × 30.3 ≅ about 5.727 ms
When BER is set, it is not cleared even if EN is set to 0. Clear BER, and then retransmit it.
2
C interface is stopped if:
2
C bus during data transfer (including the ACK bit)
2
C bus while the bus is idle is detected.
between the point where EN is set to 1
CCP
2
CHAPTER 15 I
C INTERFACE
2
C interface may run quickly,
313
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