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Delayed Interrupt Module
Block Diagram of the Delayed Interrupt Module
Delayed Interrupt Module Registers
Demand Transfer
................................................ 372
Demand Transfer
Demand Transfer 2-Cycle Transfer
Demand Transfer Fly-by Transfer
Read and Write Timing Diagrams for DMA Demand
............................................... 422
Transfer
Timing to Stop a Demand Transfer Request and Timing to
Invalidate the DREQ Pin Input
DEOP
Pin Function of the DACK, and DEOP, and DREQ Pins
.......................................................... 340
Timing of the DEOP Pin Output
Detection
........................................................ 235
0 Detection
........................................................ 235
1 Detection
........................................ 236
Change Point Detection
Detection of USB Connector Connection and Disconnection
.......................................................... 446
Examples of Vertical Synchronization Detection Operation
.......................................................... 550
........................................ 553
Field Detection Control
....................................... 311
Slave Address Detection
Vertical Synchronization Detection
Detection Result Register
Detection Result Register (BSRR)
Device Initialization
Reset (Device Initialization)
Device State Control
............................................ 104
Device State Control
Device States
Transition of Device States
DICR
Delayed Interrupt Control Register
(DICR: Delayed Interrupt Control Register)
.......................................................... 229
.............................................. 230
DLYI Bit of DICR
Dimensions
Dimensions of the MB91319
Direct Addressing Instructions
Direct Addressing Instructions
Display Control Command
Display Control Command
Display Control Command List
List of Display Control Commands
Display Example
Applied Display Examples
........................ 487, 489, 493, 561
Display Example
Display Examples
.......... 482, 516, 518, 520, 522, 525, 527
Display Format
................................................... 507
Display Format
Display Memory
Display Memory and Display Screen
Writing to Display Memory
728
........ 228
........................ 229
......................... 347
........................... 348
.................. 365
............................. 368
......................... 549
.......................... 234
.................................... 67
................................... 105
..................................... 8
............................... 719
.................................... 609
.............................. 610
......................... 570
.................................... 484
....................... 476
................................... 477
Display Output Control
Command 5-00 (Display Output Control 1)
Command 5-1 (Display Output Control 2)
Display Period
Command 14-0 (Display Period Control 1)
Command 14-1 (Display Period Control 2)
Command 14-2 (Display Period Control 3)
Command 14-3 (Display Period Control 4)
Horizontal Display Period Control
Vertical Display Period Control
Display Position
Command 5-2 (Vertical Display Position Control)
................................................. 579, 618
Command 5-3 (Horizontal Display Position Control)
................................................. 579, 618
Display Position Control
Display Position Control of Screen Background Characters
......................................................... 469
Display Position Control of Screen Background Color
......................................................... 470
Display Position Control of Sprite Characters
Display Position Control on the Main/CC Screen
Display Position Offset
Screen Display Position Offset
Display Screen
Display Memory and Display Screen
Display Signal
Display Signal Output Timing
Example of Display Signal Output (1)
Example of Display Signal Output (2)
DIVR
Base Clock Division Setting Register 0 (DIVR0)
Base Clock Division Setting Register 1 (DIVR1)
DLYI Bit
.............................................. 230
DLYI Bit of DICR
DMA
Clearing Peripheral Interrupts by DMA
Example of Controlling DMA Reception
Example of Controlling DMA Transmission
Read and Write Timing Diagrams for DMA Block/
........................................ 421
Step Transfer
Read and Write Timing Diagrams for DMA Demand
............................................... 422
Transfer
.............................................. 356
Suppressing DMA
DMA Controller
DMA Controller (DMAC) Registers
DMAC (DMA Controller)
DMA IN Transfer
............................................... 419
DMA IN Transfer
DMA OUT Transfer
............................................ 420
DMA OUT Transfer
DMA Reception
Example of Controlling DMA Reception
DMA Transfer
DMA Transfer and Interrupts
DMA Transfer during Sleep
DMA Transfer Request during External Hold
External Hold Request During DMA Transfer
.............. 616
................ 617
....... 593, 621
....... 594, 621
....... 594, 621
....... 595, 622
.......................... 560
............................. 559
............ 471
....... 465
.............................. 473
...................... 476
............................... 556
..................... 556
..................... 558
......... 95
......... 96
................... 359
................. 432
............. 433
....................... 322
........................................ 3
................. 432
................................ 356
.................................. 362
............ 357
........... 357
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