Fujitsu MB91319 Series Hardware Manual page 427

Fr60 32-bit microcontroller
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■ CONT10
The address of the CONT10 register is 0006_0034
Figure 17.2-24 shows the CONT10 register.
Address:0006-0034
Table 17.2-17 lists the bits of the CONT10 register and their functions.
Table 17.2-17 Bits of the CONT10 Register
Bit name
LSTDn
(n: 0, 2, 3)
ODDn
(n: 0, 2, 3)
TTCNTEN
TRCNTEN
DMAMODE
NULLSETn
(n: 0, 2, 3)
DREQCNT
The LSTD bit need not be reset by the CPU because the bit is reset automatically at reception of
an ACK signal after the last packet has been transmitted. The ODD bit need not be reset by the
CPU because the bit is reset automatically after the last data has been written.
The NULLSET bit is valid for the data stage of control transfer and for BULK IN transfer interrupt
IN transfer. If the NULLSET bit is set to 1, a null packet is transmitted automatically in response
to the transfer request after the last packet is transmitted when the size of the last packet is equal
to the maximum packet size. Note that the NULLSET bit does not control the transmission of 0-
Figure 17.2-24 CONT10 Register
15
14
13
12
11
D
O
O
O
N
H
R
D
D
D
U
E
D
D
D
L
Q
3
2
0
L
C
S
N
E
T
T
3
R/W R/W R/W R/W R/W R/W R/W
Polarity
ActiveHigh
ActiveHigh
ActiveHigh
ActiveHigh
-
ActiveHigh
-
.
H
10
9
8
7
6
5
N
N
D
L
L
U
U
M
S
S
L
L
A
T
T
L
L
M
D
D
S
S
O
3
2
E
E
D
T
T
E
2
0
R/W R/W R/W R/W R/W
The LSTDn bit is used to report writing of the last packet to
end point n.
This bit is set before writing the last data.
This bit is used to report writing of a short packet having an
odd byte count.
This bit is set before writing the last data.
This bit is used to enable the total send byte counter.
This bit is used to enable the total receive byte counter.
Select a transfer method of DMA.
1: Single transfer, 0: Block transfer
This bit is set to 1 for automatic transmission of a null packet.
Control DREQ assertion after the data transfer for number of
total transfer byte is ended.
1: After the data transfer for number of total transfer byte is
ended, DREQ is not asserted until number of byte for next
total transfer is set .
0: After the data transfer for number of total transfer byte is
ended, DREQ is asserted.
CHAPTER 17 USB FUNCTION
4
3
2
1
0
L
T
T
S
R
T
T
C
C
D
N
N
00000000X00000XX
0
T
T
E
E
N
N
Function
Initial value
B
405

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