Fujitsu MB91319 Series Hardware Manual page 285

Table 14.2-7 shows the data format of a frame.
Table 14.2-7 Data Format of Frame
A/D
0
1
[bit2] REC (Receiver Error Clear)
Write 0 to this bit to clear the error flags (PE, ORE, and FRE) in the SSR register.
Writing 1 to this bit has no effect. 1 is always read from this bit.
[bit1] RXE (Receiver Enable)
This bit controls the UART receive operation.
Table 14.2-8 shows the UART receive operation.
Table 14.2-8 UART Receive Operation
RXE
0
1
Note:
If a receive operation is disabled while it is in progress (while data is being input to the receive shift
register), reception of the frame is completed. The receive operation is stopped when the received
data is stored in the receive data buffer register (SIDR).
[bit0] TXE (Transmitter Enable)
This bit controls the UART send operation.
Table 14.2-9 shows the UART send operation.
Table 14.2-9 UART Send Operation
TXE
0
1
Note:
If a send operation is disabled while it is in progress (while data is being output from the transmission
register), sending is stopped when no more send data is stored in the send data buffer register
(SODR).
Data format of frame
Data frame [initial value]
Address frame
Enabling or disabling the receive operation
Disables receive operation.
Enables receive operation.
Enabling or disabling send operation
Disables send operation.
Enables send operation.
[initial value]
[initial value]
CHAPTER 14 UART
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