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CHAPTER 1 OVERVIEW
1.1
Features
The FR family is a single-chip microcontroller that has a 32-bit high-performance RISC
CPU as well as built-in I/O resources for embedded controllers requiring high-
performance and high-speed CPU processing.
The FR family is the most suitable for embedded applications, for example, TV and PDP
control, that require a high level of CPU processing performance.
This model is an FR60 series model that is based on the FR30/40-family of CPUs. It has
enhanced bus access and is optimized for high-speed use.
■ FR CPU
•
32-bit RISC, load/store architecture, five stages pipeline
•
Operating frequency of 40 MHz [PLL used, original oscillation at 10 MHz]
•
16-bit fixed-length instructions (basic instructions), one instruction per cycle
•
Memory-to-memory transfer, bit processing, instructions including barrel shift, etc.:
•
Function entry and exit instructions, multi load/store instructions:
•
Register interlock function to facilitate assembly-language coding
•
Built-in multiplier/instruction-level support
•
Signed 32-bit multiplication: 5 cycles
•
Signed 16-bit multiplication: 3 cycles
•
Interrupts (saving of PC and PS): 6 cycles, 16 priority levels
•
Harvard architecture enabling simultaneous execution of both program access and data
access
•
4-word queues in the CPU provided to add an instruction prefetch function
•
Instructions compatible with the FR family
■ Bus Interface
This bus interface is used for macro connections (USB and OSDC).
•
Maximum operating frequency of 20 MHz
•
16-bit data input-output (interface with USB and OSDC)
•
Totally independent 8-area chip select outputs that can be defined in the minimum units of
64K bytes
The CS1, CS2, and CS3 areas are reserved as shown below.
•
CS1 area: Reserved
•
CS2 area: USB function
•
CS3 area: OSDC
•
Basic bus cycle (2 cycles)
2
instructions appropriate for embedded applications
instructions compatible with high-level languages
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