Table of Contents
Advertisement
CHAPTER 17 USB FUNCTION
Notes:
3. For reading by the CPU, data is read from bit15 to bit0 of the DATAO register in units of 2 bytes.
Writing by protocol
engine
FIFO pointer
4. If the data size of a packet normally received during BULK OUT transfer is 0 bytes, the macro
program does not generate any interrupt.
■ Control Transfer (Data Stage), Bulk Transfer, or INTERRUPT IN Transfer
The data written from the local bus interface to the FIFO buffer for IN transfer at an end point is
transferred by the protocol engine to the USB bus.
Figure 17.3-4 shows the flow of control transfer (data stage), bulk transfer, and INTERRUPT IN
transfer.
Figure 17.3-4 Flow of Control Transfer (Data Stage), Bulk Transfer, and INTERRUPT IN Transfer
(4)
USB
The flow shown by the figure is explained below.
(1) Before the IN transfer to the USB, data is written from the CPU interface to the FIFO buffer for
an end point by a write operation.
414
Via CPU interface
. . . . .
62
16
14
. . . . .
63
17
15
. . . . .
31
8
7
Protocol
engine
12
10
8
6
4
2
13
11
9
7
5
3
6
5
4
3
2
1
FIFO buffers for
end points
(3)
Control
and
status
registers
FIFO buffer for
0
1
end point
0
(1)
(2)
Advertisement
Table of Contents
