Plla Clock Control (Commands 18-0 To 18-3) - Fujitsu MB91319 Series Hardware Manual

Fr60 32-bit microcontroller
Table of Contents

Advertisement

18.4.19 PLLA Clock Control (Commands 18-0 to 18-3)

Command 18-0, command 18-1, command 18-2 and command 18-3 are the commands
that control the clock of PLLA.
■ Command 18-0 (PLLA Clock Control 1-1)
❍ Address: 060
❍ Format
15
14
13
0
0
0
DAP4-DAP0:
❍ [Function]
This command controls the clock of PLLA (prescaler A[1/(2 × DAP):CKA]).
■ Command 18-1 (PLLA Clock Control 1-2)
❍ Address: 062
❍ Format
15
14
13
0
0
0
DBP4-DBP0:
❍ [Function]
This command controls the clock of PLLA (prescaler B[1/(2 × DBP):CKB]).
H
12
11
10
9
0
0
0
0
Number of PLLA clock dividing frequency 1
(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)
H
12
11
10
9
0
0
0
0
Number of PLLA clock dividing frequency 2
(Unit of dividing frequency: MIN=1 dividing frequency, MAX=62 dividing frequency)
8
7
6
5
0
0
0
0
DAP4 DAP3 DAP2 DAP1 DAP0
8
7
6
5
0
0
0
0
DBP4 DBP3 DBP2 DBP1 DBP0
CHAPTER 18 OSDC
4
3
2
1
4
3
2
1
0
0
601

Advertisement

Table of Contents
loading

Table of Contents