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[bit10, bit9] WS1, WS0 (watch timer interval select 1, 0)
These bits select the interval of the interval timer.
One of the following three intervals is selected according to the output bits of the main clock
oscillation stabilization wait timer counter:
WS1
0
0
1
1
•
These bits are cleared to 00 by a reset (INIT) request.
•
Data can be written to and read from these bits.
[bit8] WCL (watch timer clear)
Writing 0 to this bit clears the main clock oscillation stabilization wait timer to 0.
•
Only 0 can be written to this bit. Writing 1 to this bit does not affect timer operation.
•
The value read from this bit is always 1.
■ Main Clock Oscillation Stabilization Wait Timer Interrupt
If the set interval time elapses while the main clock oscillation stabilization wait timer counter is
counting with the main clock, the main clock oscillation stabilization wait timer interrupt flag (WIF)
is set to 1. Then, if the main clock oscillation stabilization wait timer interrupt enable bit (WIE) is
set to 1 (interrupt output is enabled), an interrupt request is output to the CPU. Note that watch
interrupts do not occur when main clock oscillation is stopped (see the next Item, "■Operation of
Interval Timer Function") because counting is stopped when the main clock is stopped.
To clear an interrupt request, write 0 to the WIF bit by the interrupt processing routine. Note that
the WIF bit is set to 1 at the trailing edge of the selected frequency-divide output regardless of the
value of the WIE bit.
Note:
The WIF and WCL bits must be cleared to 0 (WIF=WCL=0) at the same time if main clock oscillation
stabilization wait timer interrupt output is to be enabled (WIE = 1) or the value of the WS1 and WS0
bits are to be changed after release from the reset state.
Reference:
• If the WIE bit is changed from 0 to 1 to enable interrupt output when the WIF bit is 1, an interrupt
request is output immediately.
• If a counter clear (WCL bit of WPCR is 1) and overflow of selected bits occur at the same time,
the WIF bit is not set to 1.
WS0
Interval timer interval (at F
0
Setting prohibited
12
(410 µs) (default value)
1
2
/F
CL
17
0
2
/F
(13.1 ms)
CL
23
1
2
/F
(839 ms)
CL
CHAPTER 3 CPU AND CONTROL UNITS
= 10 MHz)
CL
123
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