Flash Memory Wait Register (Flwc) - Fujitsu MB91319 Series Hardware Manual

CHAPTER 19 FLASH MEMORY
19.2.2

Flash Memory Wait Register (FLWC)

The flash memory wait register (FLWC) controls the wait status of flash memory in CPU
mode.
■ Configuration
Figure 19.2-3 shows the bit configuration of flash memory wait register (FLWC).
Figure 19.2-3 Bit Configuration of Flash Memory Wait Register (FLWC)
00007004
[bit7, bit6] Reserved
These are reserved bits. Always set these bits to "0."
[bit5, bit4] FAC1 and FAC0
These bits specify the H width of ATDIN and EQIN.
FAC1
0
0
1
1
[bit3] Reserved
This is a reserved bit. Always set this bit to "0."
[bit2 to bit0] WTC2, WTC1, and WTC0 (wait cycle bits)
These bits control the wait status of flash memory.
WTC2
0
0
0
0
1
1
1
1
640
bit7 bit6
FAC1
H
R R/W
(0) (1)
FAC0
0
1
0
1
WTC1
0
0
1
1
0
0
1
1
bit5 bit4 bit3
FAC0
R/W R/W R/W
(1) (1) (0)
ATDIN EQIN
0.5 clock 1.0 clock
1.0 clock 1.5 clock
1.5 clock 2.0 clock
0.5 clock 1.5 clock
WTC0 Wait cycle
0 Setting is disabled.
1
0
1
0
1
0
1
bit2 bit1 bit0
WTC2 WTC1 WTC0
R/W R/W R/W
(0) (1) (0)
40 MHz (Initial value)
1
2 40 MHz (Initial value)
3
4
5
6
7