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■ Example of Controlling DMA Transmission
❍ Transmission operation
Figure 17.3-14 shows an example of controlling DMA transmission.
Figure 17.3-14 Example of Controlling DMA Transmission
Start of transmission operation
Write total send byte count
to TTSIZE (control register)
Set the TTCNTEN bit of
CONT10 (control register)
to 1
Clear the FIFOBUSY2 bit of
CONT4 (control register) to 0
Set the DFIFOBUSY2 bit of
CONT5 (control register) to 1
Set the MDREQ2 bit of
CONT6 (control register)
to 1
Is DREQ asserted?
YES
Write send data (2 bytes) to
FIFO buffer for transmission
Is IRQ asserted?
YES
Read the interrupt source bit
(TTRSEND) of ST5
(status register)(*1)
End of transmission operation
To use the total send byte counter,
perform these operations before
writing data to the FIFO buffer.
NO
NO
*: No interrupts occur if the total send
byte counter is not used. The end of
total data transfer must be determined
by a method other than the macro program.
CHAPTER 17 USB FUNCTION
433
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