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CHAPTER 18 OSDC
•
Figure 18.3-6 shows the input timing of vertical synchronization signal (VSYNC pin input
signal) and horizontal synchronization signal (HSYNC pin input signal) for interlacing display.
[Field A detection timing]
Horizontal
synchronous
signal
Vertical
synchronization
signal
[Field B detection timing]
Horizontal
synchronous
signal
Vertical
synchronization
signal
Note:
The display raster of the font which is displayed in each field during interlacing, see "18.3.5
Synchronization Control".
554
Figure 18.3-6 Field Detection Timing
H/4
H/4
H/4
H/4
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