Operation From Starting To End/Stopping - Fujitsu MB91319 Series Hardware Manual

Fr60 32-bit microcontroller
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CHAPTER 16 DMA CONTROLLER (DMAC)
16.3.9

Operation from Starting to End/Stopping

Starting of DMA transfer is controlled independently for each channel, but before
transfer starts, the operation of all channels needs to be enabled. This section
describes operation from starting to end/stopping.
■ Operation Start
❍ Enabling operation for all channels
Before activating each DMAC channel, operation for all channels needs to be enabled in advance
with the DMA operation enable bit (DMAE of DMACR). All start settings and transfer requests that
occurred before operation is enabled are invalid.
❍ Starting transfer
The transfer operation can be started by the operation enable bit of the control register for each
channel. If a transfer request to an activated channel is accepted, the DMA transfer operation is
started in the specified mode.
❍ Starting from a temporary stop
If a temporary stop occurs before starting with channel-by-channel or all-channel control, the
temporary stopped state is maintained even though the transfer operation is started. If transfer
requests occur in the meantime, they are accepted and retained. When temporary stopping is
released, transfer is started.
■ Transfer Request Acceptance and Transfer
Sampling for transfer requests set for each channel starts after starting.
If edge detection is selected for the external pin start source and a transfer request is detected,
the request is retained within DMAC until the clear conditions are met (when the external pin start
source is selected for block, step, or burst transfer).
If level detection or peripheral interrupt start is selected for the external pin start source, DMAC
continues the transfer until all transfer requests are cleared. When they are cleared, DMAC stops
the transfer after one transfer unit (demand transfer or peripheral interrupt start).
Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle
the interrupts.
Transfer requests are always accepted while other channel requests are being accepted and
transfer performed. The channel that will be used for transfer is determined for each transfer unit
after priority has been checked.
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