Fujitsu MB91319 Series Hardware Manual page 598

Fr60 32-bit microcontroller
Table of Contents

Advertisement

CHAPTER 18 OSDC
■ Command 4 (Line Control Data Set 2)
❍ Address: 008
❍ Format
15
14
13
0
0
0
LDS:
Line character output control
(0: Off, 1: ON)
LGY1, LGY0:
Line vertical enlargement control
(0, 0: Normal)
(0, 1: Double height)
(1, 0: Setting prohibited)
(1, 1: Quadruple height)
LGX1, LGX0:
Line horizontal enlargement control
(0, 0: Normal)
(0, 1: Double width)
(1, 0: Setting prohibited)
(1, 1: Quadruple width)
❍ [Function]
Command 4 writes the above setting data to the area of line VRAM specified by command 0
(VRAM write address set 1), along with the line control data set by command 3 (line control data
set 1).
❍ [Supplement]
The shaded background succeeding line merge control bit (LD) has different effects on the
character shaded backgrounds and line shaded backgrounds.
Shaded Background Succeeding Line Merge Display (Line Background)".
Notes:
• Since reset input makes the contents of the entire area of VRAM undefined, be sure to set VRAM
before display.
• Issuing this command does not automatically increment the VRAM write address. For each line to
be set, set the address using command 0.
576
H
12
11
10
9
LDS LGY1 LGY0 LGX1 LGX0 LD
8
7
6
5
LE
LM1
LM0
LE:
Character background extension
control
(0: Normal, 1: Extended)
LD:
Shaded background succeeding
line merge control
(0: Independent, 1: Merge with
the next line)
LM1, LM0:
Line background control
(0, 0: OFF)
(0, 1: Solid-fill display)
(1, 0: Concaved, shaded display)
(1, 1: Convexed, shaded display)
L3 to L0:
Line background color
(From among 16 colors)
4
3
2
1
L3
L2
L1
For details, see "18.2.11.1
0
L0

Advertisement

Table of Contents
loading

Table of Contents