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Wait Time after Changing the PLL Multiply-by Rate
Wait Time after Enabling a PLL
PLLA Clock
Command 18-0 (PLLA Clock Control 1-1)
Command 18-1 (PLLA Clock Control 1-2)
Command 18-2 (PLLA Clock Control 2)
Command 18-3 (PLLA Clock Control 3)
PLLB Clock
Command 18-4 (PLLB Clock Control 1-1)
Command 18-5 (PLLB Clock Control 1-2)
Command 18-6 (PLLB Clock Control 2)
Command 18-7 (PLLB Clock Control 3)
PLLC Clock
Command 18-10 (PLLC Clock Control 2)
Command 18-11 (PLLC Clock Control 3)
Command 18-8 (PLLC Clock Control 1-1)
Command 18-9 (PLLC Clock Control 1-2)
Port Data Registers
Configuration of the Port Data Registers (PDR)
Port Function Registers
Configuration of the Port Function Registers (PFR)
.......................................................... 132
Initial Values and Functions of the Port Function Registers
................................................ 133
(PFRs)
Power Supply
................................................ 24
Power Supply Pins
Power-Off
Precautions at Power-On/Power-Off
Power-On
............................................................ 25
Power-on
Precautions at Power-On/Power-Off
Source Oscillation Input at Power-on
Wait Time after Power-On
PPG
..................................................................... 4
PPG
PPG Output All-L and All-H
PPG Cycle Setting Register
Bit Configuration of PPG Cycle Setting Register (PCSR)
.......................................................... 159
PPG Duty Setting Register
Bit Configuration of PPG Duty Setting Register (PDUT)
.......................................................... 160
PPG Timer
Block Diagram for One Channel of PPG Timer
Characteristics of PPG Timer
Overall Block Diagram of PPG Timer
Precautions on Using the PPG Timer
Registers of the PPG Timer
PPG Timer Register
Bit Configuration of PPG Timer Register (PTMR)
Precautions
Precautions on Using the 16-bit Reload Timer
Priority
Priority Among Channels
................................................ 211
Priority Decision
Priority of EIT Causes To Be Accepted
Priority of State Transition Requests
.... 78
............................... 78
............... 601
............... 601
.................. 602
.................. 602
............... 603
............... 603
.................. 604
.................. 604
................ 605
................ 606
............... 605
............... 605
......... 130
......................... 25
......................... 25
........................ 25
...................................... 78
................................. 167
......... 154
................................ 152
..................... 153
....................... 168
................................... 155
..... 161
........... 150
..................................... 363
..................... 58
....................... 109
Processing
.......................................237
Save/Restore Processing
Program Access
....................................................44
Program Access
Programmer
System Configuration of AF220/AF210/AF120/AF110
Flash Micro-controller Programmer
Programming Mode
FR-CPU Programming Mode (16 Bits, Read/Write)
..........................................................642
Programming Model
Basic Programming Model
PTMR
Bit Configuration of PPG Timer Register (PTMR)
Pulse Width
Minimum Effective Pulse Width of the DREQ Pin Input
..........................................................365
Pulse Width Counter
16-Bit Pulse Width Counter
Registers of the 16-Bit Pulse Width Counter
PWC
....................................................................4
PWC
PWC Control Register
PWC Control Register (PWCCH)
PWC Control Register (PWCCL)
PWC Control Register 2 (PWCC2)
PWC Data Register
PWC Data Register (PWCD)
PWCC
PWC Control Register 2 (PWCC2)
PWCCH
PWC Control Register (PWCCH)
PWCCL
PWC Control Register (PWCCL)
PWCD
PWC Data Register (PWCD)
PWCUD
Upper Value Setting Register (PWCUD)
PWM Mode
.......................................................162
PWM Mode
PWM Mode Timing Chart
Q
Quartz Oscillation Circuit
Quartz Oscillation Circuit
R
RAM
.........................................................3
Built-in RAM
FONT RAM Memory Map
Palette RAM Configuration
Writing a Single Character to Character RAM
...........................................479
Writing to Line RAM
RDY
Ready/Busy Signal (RDY/BUSYX)
............667
......................................36
......161
...................................190
..............191
...........................194
............................192
..........................197
.................................196
..........................197
...........................194
............................192
.................................196
..................198
.....................................162
........................................24
....................................626
...................................480
...........477
.........................648
735
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