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❍ CPU
The CPU is a compact implementation of the 32-bit RISC FR architecture.
Five instruction pipe lines are used to execute one instruction per cycle. A pipeline consists of the
following stages:
•
Instruction fetch (IF): Outputs an instruction address to fetch an instruction.
•
Instruction decode (ID): Decodes a fetched instruction. Also reads a register.
•
Execution (EX): Executes an arithmetic operation.
•
Memory access (MA): Performs a load or store access to memory.
•
Write-back (WB): Writes an operation result (or loaded memory data) to a register.
CLK
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instructions are never executed randomly. If Instruction A enters a pipeline before Instruction B, it
always reaches the write-back stage before Instruction B.
In general, one instruction is executed per cycle. However, multiple cycles are required to
execute a load/store instruction with a memory wait, a branch instruction without a delay slot, or a
multiple-cycle instruction. The execution of instructions slows down if the instructions are not
supplied fast enough.
❍ 32-bit/16-bit bus converter
The 32-bit/16-bit bus converter provides an interface between the F-bus accessed with 32-bit
width and the R-bus accessed with 16-bit width and enables data access from the CPU to built-in
peripheral circuits.
If the CPU performs a 32-bit width access to the R bus, this bus converter converts the access
into two 16-bit width accesses. Some of the built-in peripheral circuits have limitations on the
access bus width.
❍ Harvard/Princeton bus converter
The Harvard/Princeton bus converter coordinates instruction and data accesses of the CPU to
provide a smooth interface between it and external buses.
The CPU has a Harvard architecture with separate buses for instructions and data. On the other
hand, the bus controller that performs control of external buses has a Princeton architecture with
a single bus. The Harvard/Princeton bus converter assigns priorities to instruction and data
accesses from the CPU to control accesses to the bus controller. This function allows the order of
external bus accesses to be permanently optimized.
Figure 3.2-2 Instruction Pipelines
WB
MA
WB
EX
MA
WB
ID
EX
MA
IF
ID
EX
IF
ID
CHAPTER 3 CPU AND CONTROL UNITS
WB
MA
WB
EX
MA
WB
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