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CHAPTER 5 16-BIT RELOAD TIMER
[bit5] OUTL
This bit sets the output level of the TOUT pin. The pin levels are reversed while this bit is set
to "0" and "1". Specify an output waveform using a combination of this bit, bit4 (RELD bit), and
the corresponding bit of the PFR register of the I/O port. Table 5.2-4 shows the settings when
these bits are combined.
Table 5.2-4 Settings of TOEx, OUTL, and RELD
TOEx
0
1
1
1
1
× in the table indicates an arbitrary value.
TOEx indicates TOE0 to TOE3 in PFR (Port Function Register).
[bit4] RELD
This bit is the reload enable bit. If it is set to "1", reload mode is entered. As soon as the
counter value underflows from 0000
into the counter and the count operation is continued.
If this bit is set to "0", the count operation is stopped when the counter value underflows from
0000
[bit3] INTE
This bit is the interrupt request enable bit. If the INTE bit is set to "1", an interrupt request is
generated when the UF bit is set to "1". If it is set to "0", no interrupt request is generated.
[bit2] UF
This bit is the timer interrupt request flag. This bit is set to "1" when the counter value
underflows from 0000
Writing "1" to this bit is meaningless. When this bit is read by a read modify write instruction,
"1" is always read.
[bit1] CNTE
This bit is the count enable bit of the timer. Write "1" to this bit to enter the start trigger wait
state. Write "0" to this bit to stop the count operation.
[bit0] TRG
This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load the
contents of the reload register into the counter, and start the count operation.
Writing "0" to this bit is meaningless. The read value is always "0".
The trigger input to this register is valid only if CNTE=1. No operation occurs if CNTE=0.
142
OUTL
RELD
×
×
0
0
1
0
0
1
1
1
to FFFF
.
H
H
to FFFF
H
Output waveform
Output prohibited
"H" level square wave while counting is in progress
"L" level square wave while counting is in progress
"L" level toggle output while the counting is started
"H" level toggle output while the counting is started
to FFFF
, the contents of the reload register are loaded
H
H
. Write "0" to this bit to clear it.
H
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