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2
CHAPTER 15 I
C INTERFACE
• Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur
When an instruction which generates a start condition by enabling I
executed (set 1 to MSS bit in IBCR register) with the I
This is because, as shown in Figure 15.2-5, when the other master on the I
communication with I
condition detected (BB bit =0).
Figure 15.2-5 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
SCL pin
SDA pin
EN bit
MSS bit
AL bit
BB bit
INT bit
If a symptom as described above can occur, follow the procedure below for software processing.
1. Execute the instruction that generates a start condition (set the MSS bit to 1)
2. Use, for example, the timer function to wait for the time for three-bit data transmission at the
2
I
C transfer frequency set in the ICCR register.*
Example:
3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are 1 and 0,
respectively, set the EN bit in the ICCR register to 0 to initialize I
are not so, perform normal processing.
296
2
C disabled (EN bit=0), the I
INT bit interruption is not generated
Start Condition
in 9th clock.
SLAVE ADDRESS
Time for three-bit data transmission at an I
3
)}x30=30 µs
(100x10
2
2
C bus occupied by another master.
2
C bus enters the occupied state with no start
ACK
DAT
2
C transfer frequency of 100 kHz = {1/
2
C. When the AL and BB bits
C operation (EN bit=1) is
2
C bus starts
Stop Condition
ACK
0
0
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