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CHAPTER 16 DMA CONTROLLER (DMAC)
[bit29 to bit28] MOD (MODe)*: Transfer mode setting
These bits specify the operation mode of the corresponding channel as shown in Table 16.2-
6.
Table 16.2-6 Settings for Transfer Modes
MOD
00
01
10
11
•
When reset: Initialized to 00.
•
These bits are readable and writable.
[bit27 to bit26] WS (Word Size)*: Transfer data width selection
These bits are used to select the transfer data width of the corresponding channel. Transfer
operations are repeated in units of the data width specified in this register for as many times
as the specified count.
Table 16.2-7 shows the specification of the transfer data width.
Table 16.2-7 Selection of the Transfer Data Width
WS
00
01
10
11
•
Setting disabled
•
When reset: Initialized to 00.
330
Block/step transfer mode (initial value)
Burst transfer mode
Demand transfer mode
Setting disabled
Byte-width transfer
(initial value)
Halfword-width transfer
Word-width transfer
Setting disabled
Function
Function
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