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■ No-coprocessor Trap
If a coprocessor instruction using a coprocessor that is not installed is executed, a no-
coprocessor trap occurs.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of next instruction → (SSP)
5. "0" → S flag
6. (TBR+3E0
■ Coprocessor Error Trap
If an error occurs while a coprocessor is being used and then a coprocessor instruction that
operates on the coprocessor is executed, a coprocessor error trap occurs.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. Address of next instruction → (SSP)
5. "0" → S flag
6. (TBR+3DC
■ Operation of RETI Instruction
The RETI instruction specifies return from the EIT processing routine.
[Operation]
1. (R15) → PC
2. R15+4 → R15
3. (R15) → PS
4. R15+4 → R15
The RETI instruction must be executed while the S flag is set to 0.
■ Precaution on Delay Slot
A delay slot for a branch instruction has restrictions regarding EIT.
See "3.7 Branch Instructions".
) → PC
H
) → PC
H
CHAPTER 3 CPU AND CONTROL UNITS
63
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