Fujitsu MB91319 Series Hardware Manual page 428

Fr60 32-bit microcontroller
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CHAPTER 17 USB FUNCTION
byte packets in the status stage of control transfer.
The LSTD2 bit provides two sides of registers corresponding to the double-buffer configuration.
The sides of the LSTD2 bit are switched at the same time as buffer switching. The side of the
CONT10 register currently available for reading and writing by an application program
corresponds to the side of the FIFO registers currently available for reading and writing.
The LSTD2 has the above function. When the value of the LSTD2 bit changes from 1 to 0, it
does not mean that transfer of the last packet ended.
If the NULLSET bit is 1, an interrupt by an ACK signal is asserted when transfer of null packets
ends with an ACK signal (when an ACK signal is received). If the NULLSET bit is 0, an interrupt
by an ACK signal is asserted when transfer of the last packet ends with an ACK signal (when an
ACK signal is received).
Each bit of LSTD and 0DD is valid by writing 1. Writing 0 is disabled.
■ TTSIZE
The TTSIZE register is used to set and count the total send byte count for BULK IN transfer. The
address of the TTSIZE register is 0006_0036
Figure 17.2-25 shows the TTSIZE register.
Address:0006-0036
The TTSIZE register (counter) counts down each time send data is written to the FIFO buffer for
transmission.
To use the TTSIZE counter, set a value other than 0000
CONT10, TTCNTEN, then start write access to the FIFO buffer. Do not start write access to the
FIFO buffer when 0000
TTSIZE sets MDREQ2 of CONT6 to 0 and DREQ2 to masked state.
406
Figure 17.2-25 TTSIZE Register
15
14
13
12
11
10
H
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
is set in the TTSIZE register and the CONT10, TTCNTEN is 1.
H
.
H
9
8
7
6
5
4
in the TTSIZE register, write 1 to the
H
3
2
1
0
Initial value
0001000100010001
B

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