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APPENDIX I Instruction Lists
■ Memory Load Instructions
Table I.2-8 Memory Load Instructions
Mnemonic
LD
@Rj, Ri
LD
@(R13,Rj), Ri
LD
@(R14,disp10), Ri
LD
@(R15,udisp6), Ri
LD
@R15+, Ri
LD
@R15+, Rs
LD
@R15+, PS
LDUH @Rj, Ri
LDUH @(R13,Rj), Ri
LDUH @(R14,disp9), Ri
LDUB @Rj, Ri
LDUB @(R13,Rj), Ri
LDUB @(R14,disp8), Ri
*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL
Note:
In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as
shown below:
disp10/4 → o8, disp9/2 → o8, disp8 → o8; disp10, disp9, and disp8 have a sign.
udisp6/4 → o4; udisp6 has no sign.
710
Type
OP
CYCLE
A
04
b
A
00
b
B
20
b
C
03
b
E
07-0
b
E
07-8
b
E
07-9
1+a+b
A
05
b
A
01
b
B
40
b
A
06
b
A
02
b
B
6
b
NZVC
Operation
→
----
(Rj)
Ri
→
----
(R13+Rj)
Ri
→
----
(R14+disp10)
→
----
(R15+udisp6)
→
----
(R15)
Ri,R15+=4
→
----
(R15)
Rs, R15+=4
→
CCCC
(R15)
PS, R15+=4
→
----
(Rj)
Ri
→
----
(R13+Rj)
Ri
→
----
(R14+disp9)
→
----
(Rj)
Ri
→
----
(R13+Rj)
Ri
→
----
(R14+disp8)
Remarks
Ri
Ri
Rs: Special register
Zero extension
Zero extension
Ri
Zero extension
Zero extension
Zero extension
Ri
Zero extension
*
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