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CHAPTER 3 CPU AND CONTROL UNITS
[Circuits that do not stop in the stop state]
•
Oscillation circuits that are set not to stop
•
If 0 is set for bit1 (OSCD2 bit) of the standby control register (STCR), the subclock
oscillation circuit in the stop state is not stopped.
•
If 0 is set for bit0 (OSCD1 bit) of the standby control register (STCR), the main clock
oscillation circuit in the stop state is not stopped.
•
PLL connected to the oscillation circuit that is enabled and is not set to stop
•
If 0 is set for bit1 (OSCD2 bit) of the standby control register (STCR) and 1 is set for bit11
(PLL2EN bit) of the clock source control register (CLKR), the subclock PLL in the stop state
is not stopped.
•
If 0 is set for bit0 (OSCD1 bit) of the standby control register (STCR) and 1 is set for bit10
(PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in the stop
state is not stopped.
[High impedance control of a pin in the stop state]
If 1 is set for bit5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stop
state is set to the high impedance state.
See "APPENDIX H Pin State List" for the pins subject this type of control.
If bit5 (HIZ bit) of the standby control register (STCR) is set to 0, the pin outputs in the stop state
maintain the values set before transition to the stop state.
For details see "APPENDIX H Pin State List".
[Sources of return from the stop state]
•
Generation of a specific valid interrupt request (not requiring a clock)
Only the external interrupt input pins (INTn pins), main clock oscillation stabilization wait timer
interrupt during main clock oscillation, and watch interrupt during subclock oscillation are
enabled.
If an interrupt request with an interrupt level other than interrupt disabled (1F
mode is cleared and the RUN state (normal operation state) is entered.
To prevent stop mode from being cleared even when an interrupt request occurs, set interrupt
disabled (1F
•
Generation of a settings initialization reset (INIT) request
If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) is
unconditionally entered.
•
Generation of an operation initialization reset (RST)
If an operation initialization reset (RST) occurs, the operation initialization reset (RST) is
unconditionally entered.
For information about the priority of sources, see "■Priority of State Transition Requests"" in
"3.12.1 Device States and State Transitions".
[Selecting a clock source in stop mode]
Select the main clock divided by 2 as the source clock before setting stop mode. For more
information, see "3.11 Clock Generation Control" especially Section "3.11.1 PLL Controls".
The same limitations as in the normal operation apply to the setting of a divide-by rate.
112
) as the interrupt level in the corresponding ICR.
H
) occurs, stop
H
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