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If the setting in this register is changed, the new divide-by rate takes effect for the clock rate
following the one during which the setting was made.
[bit7 to bit4] T3, T2, T1, T0 (clkT divide select 3-0)
These bits are the clock divide-by rate setting bits of the external bus clock (CLKT). Set the
clock divide-by rate of the external extended bus interface clock (CLKT). The values written to
these bits determine the divide-by rate (clock frequency) of the external extended bus
interface clock in relation to the base clock, which can be selected from the 16 types shown in
Table 3.11-7.
The upper-limit frequency for operation 20 MHz. Do not set adivide-by rate that results in a
frequency exceeding this limit.
CHAPTER 3 CPU AND CONTROL UNITS
97
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