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If a user interrupt or NMI request is accepted when EIT requests are detected, the CPU operates
as follows, using an interrupt number corresponding to the accepted interrupt request.
Parentheses show an address indicated by the register.
■ Operation of INT Instruction
INT #u8
A branch to the interrupt handler for the vector indicated by u8 generation.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. PC + 2 → (SSP)
5. "0" → I flag
6. "0" → S flag
7. (TBR + 3FC
■ Operation of INTE Instruction
INTE
A branch to the interrupt handler for the vector indicated by vector number #9 generation.
[Operation]
1. SSP-4 → SSP
2. PS → (SSP)
3. SSP-4 → SSP
4. PC + 2 → (SSP)
5. "00100" → ILM
6. "0" → S flag
7. (TBR+3D8
Do not use the INTE instruction in the processing routine of the INTE instruction or a step trace
trap.
During step execution, no EIT due to INTE generation.
-4 × u8) → PC
H
) → PC
H
CHAPTER 3 CPU AND CONTROL UNITS
61
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