Fujitsu MB91319 Series Hardware Manual page 371

■ Step/Block Transfer 2-Cycle Transfer
For a step/block transfer (Transfer for each transfer request is performed as many times as the
specified block count), all 32-bit areas can be specified as the transfer source/transfer destination
address.
Table 16.3-5 shows the specifiable transfer addresses.
Table 16.3-5 Specifiable Transfer Addresses (for Step/Block Transfer 2-Cycle Transfer)
Transfer source addressing
All 32-bit areas specifiable
❍ Step transfer
If 1 is set as the block size, a step transfer sequence is generated.
[Features of a step transfer]
• If a transfer request is received, the transfer request is cleared after one transfer operation
and then the transfer is stopped (The DMA transfer request to the bus controller is canceled).
• Another request occurring during transfer is ignored.
• If a transfer request for another channel with a higher priority is received during transfer, the
channel is switched after the transfer is stopped and then restarted. Priority in a step transfer
is valid only if transfer requests occur simultaneously.
❍ Block transfer
If any value other than 1 is specified as the block size, a block transfer sequence is generated.
[Features of a block transfer]
• The block transfer has the same features as those of a step transfer except that one transfer
unit consists of multiple transfer cycle counts (number of blocks).
Figure 16.3-3 shows an example of block transfer.
Figure 16.3-3 Example of Demand Transfer Started by Rising Edge Detection at an External Pin. The
Transfer request ( edge)
Bus operation
Number of blocks
Transfer count
Transfer end
Number of Blocks is 2, and the Transfer Count is 2.
CPU SA DA
2
CHAPTER 16 DMA CONTROLLER (DMAC)
Direction Transfer destination addressing
=>
CPU
SA DA
1 0
2
All 32-bit areas specifiable
SA DA SA
2
1
DA
1
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