Fujitsu MB91319 Series Hardware Manual page 626

Fr60 32-bit microcontroller
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CHAPTER 18 OSDC
■ Command 18-6(PLLB Clock Control 2)
❍ Address: 06C
❍ Format
15
14
13
0
0
0
DKB11-DKB0: Number of clock dividing frequency
❍ [Function]
This command adjusts the frequency of the using dot clock.
❍ [Supplement]
This command sets the value divided until the horizontal synchronizing signal cycle to the clock
generated with prescaler C (command 18-4:DCP4-DCP0).
■ Command 18-7(PLLB Clock Control 3)
❍ Address: 06E
❍ Format
15
14
13
0
0
0
VSLB2-VSLB0:
CPEB:
CHGB1,CHGB0:
❍ [Function]
This command controls the oscillation of PLLB.
604
H
12
11
10
9
0
DKB11
DKB10
DKB9
(1 clock unit: MIN=129 clocks, MAX=4096 clocks)
H
12
11
10
9
0
0
0
0
PLLB VCO selection control
(0,0,0: VC01)
(0,0,1: VC02)
(0,1,0: VC03)
(0,1,1: VC04)
(1,0,0: VC05)
(1,0,1: VC06)
(Other setting prohibited.)
PLLB charge pump control
(0: OFF, 1: ON)
BIAS current control of PLLB charge pump
(0,0: Approx. 100 µA)
(0,1: Approx. 500 µA)
(1,0: Approx. 1mA)
(1,1: Setting prohibited.)
8
7
6
5
DKB8 DKB7 DKB6
DKB5
8
7
6
5
0
VCOB VSLB2
VSLB1
VSLB0
VCOB:
PDEB: PLLB phase comparator control
4
3
2
1
DKB4
DKB3 DKB2 DKB1
4
3
2
1
CHGB1 CHGB0 CPEB
PDEB
PLLB VC0 oscillation control
(0: OFF, 1: ON)
(0: OFF, 1: ON)
0
DKB0
0

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