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Fujitsu MB91319 Series Hardware Manual

Fujitsu MB91319 Series Hardware Manual (766 pages)

FR60 32-BIT MICROCONTROLLER  
Brand: Fujitsu | Category: Controller | Size: 4.5 MB
Table of contents
Table Of Contents11................................................................................................................................................................
Chapter 1 Overview23................................................................................................................................................................
Features24................................................................................................................................................................
Block Diagram29................................................................................................................................................................
External Dimensions30................................................................................................................................................................
Pin Layout31................................................................................................................................................................
List Of Pin Functions32................................................................................................................................................................
Input-output Circuit Forms39................................................................................................................................................................
Chapter 2 Handling The Device45................................................................................................................................................................
Precautions On Handling The Device46................................................................................................................................................................
Chapter 3 Cpu And Control Units51................................................................................................................................................................
Memory Space52................................................................................................................................................................
Internal Architecture53................................................................................................................................................................
Programming Model58................................................................................................................................................................
Data Configuration65................................................................................................................................................................
Word Alignment66................................................................................................................................................................
Memory Map67................................................................................................................................................................
Branch Instructions68................................................................................................................................................................
Eit (exception, Interrupt, And Trap)71................................................................................................................................................................
Eit Interrupt Levels72................................................................................................................................................................
Interrupt Control Unit (icr)74................................................................................................................................................................
System Stack Pointer (ssp)75................................................................................................................................................................
Table Base Register (tbr)76................................................................................................................................................................
Multiple Eit Processing80................................................................................................................................................................
Eit Operations82................................................................................................................................................................
Operating Modes86................................................................................................................................................................
Reset (device Initialization)89................................................................................................................................................................
Reset Levels90................................................................................................................................................................
Reset Sources91................................................................................................................................................................
Reset Sequence93................................................................................................................................................................
Oscillation Stabilization Wait Time94................................................................................................................................................................
Reset Operation Modes96................................................................................................................................................................
Clock Generation Control97................................................................................................................................................................
Pll Controls98................................................................................................................................................................
Oscillation Stabilization Wait Time And Pll Lock Wait Time100................................................................................................................................................................
Clock Distribution102................................................................................................................................................................
Clock Division104................................................................................................................................................................
Block Diagram Of Clock Generation Controller105................................................................................................................................................................
Register Of Clock Generation Controller106................................................................................................................................................................
Peripheral Circuits Of Clock Controller122................................................................................................................................................................
Device State Control126................................................................................................................................................................
Device States And State Transitions127................................................................................................................................................................
Low-power Modes132................................................................................................................................................................
Watch Timer136................................................................................................................................................................
Main Clock Oscillation Stabilization Wait Timer142................................................................................................................................................................
Chapter 4 I/o Port149................................................................................................................................................................
Overview Of The I/o Port150................................................................................................................................................................
I/o Port Registers152................................................................................................................................................................
Chapter 5 16-bit Reload Timer159................................................................................................................................................................
Overview Of The 16-bit Reload Timer160................................................................................................................................................................
Bit Reload Timer Registers161................................................................................................................................................................
Control Status Register (tmcsr)162................................................................................................................................................................
Bit Timer Register (tmr)165................................................................................................................................................................
Bit Reload Register (tmrlr)166................................................................................................................................................................
Bit Reload Timer Operation167................................................................................................................................................................
Chapter 6 Programmable Pulse Generator (ppg) Timer173................................................................................................................................................................
Outline174................................................................................................................................................................
Block Diagram Of The Ppg Timer175................................................................................................................................................................
Registers Of The Ppg Timer177................................................................................................................................................................
Control Status Register (pcnh, Pcnl)178................................................................................................................................................................
Ppg Cycle Setting Register (pcsr)181................................................................................................................................................................
Ppg Duty Setting Register (pdut)182................................................................................................................................................................
Ppg Timer Register (ptmr)183................................................................................................................................................................
Pwm Mode184................................................................................................................................................................
One-shot Mode186................................................................................................................................................................
Interrupts188................................................................................................................................................................
Ppg Output Of All-l And All-h189................................................................................................................................................................
Precautions On Using The Ppg Timer190................................................................................................................................................................
Chapter 7 Multifunction Timer191................................................................................................................................................................
Overview Of The Multifunction Timer192................................................................................................................................................................
Registers Of The Multifunction Timer194................................................................................................................................................................
Low-pass Filter Control Register (txlpcr)195................................................................................................................................................................
Capture Control Register (txccr)196................................................................................................................................................................
Timer Setting Register (txtcr)198................................................................................................................................................................
Entire Timer Control Register (txr)200................................................................................................................................................................
Timer Compare Data Register (txdrr)201................................................................................................................................................................
Capture Data Register (txcrr)202................................................................................................................................................................
Test Mode Register (tmode)203................................................................................................................................................................
Used Bit Description For Each Mode204................................................................................................................................................................
Multifunction Timer Operation206................................................................................................................................................................
Chapter 8 16-bit Pulse Width Counter211................................................................................................................................................................
Overview Of The 16-bit Pulse Width Counter212................................................................................................................................................................
Registers Of The 16-bit Pulse Width Counter213................................................................................................................................................................
Pwc Control Register (pwccl)214................................................................................................................................................................
Pwc Control Register (pwcch)216................................................................................................................................................................
Pwc Data Register (pwcd)218................................................................................................................................................................
Pwc Control Register 2 (pwcc2)219................................................................................................................................................................
Upper Value Setting Register (pwcud)220................................................................................................................................................................
Operation Of The 16-bit Pulse Width Counter221................................................................................................................................................................
Chapter 9 Interrupt Controller225................................................................................................................................................................
Overview Of The Interrupt Controller226................................................................................................................................................................
Interrupt Controller Registers228................................................................................................................................................................
Interrupt Control Register (icr)230................................................................................................................................................................
Hold Request Cancellation Request Level Setting Register (hrcl)232................................................................................................................................................................
Interrupt Controller Operation233................................................................................................................................................................
Example Of Using The Hold Request Cancellation Request Function (hrcr)236................................................................................................................................................................
Chapter 10 External Interrupt And Nmi Controller239................................................................................................................................................................
Overview Of The External Interrupt And Nmi Controller240................................................................................................................................................................
External Interrupt And Nmi Controller Registers241................................................................................................................................................................
Interrupt Enable Register (enir)242................................................................................................................................................................
External Interrupt Source Register (eirr)243................................................................................................................................................................
External Interrupt Request Level Setting Register (elvr)244................................................................................................................................................................
Operation Of The External Interrupt And Nmi Controller245................................................................................................................................................................
Chapter 11 Realos-related Hardware249................................................................................................................................................................
Delayed Interrupt Module250................................................................................................................................................................
Delayed Interrupt Module Registers251................................................................................................................................................................
Operation Of The Delayed Interrupt Module252................................................................................................................................................................
Bit Search Module253................................................................................................................................................................
Bit Search Module Registers254................................................................................................................................................................
Bit Search Module Operation257................................................................................................................................................................
Chapter 12 10-bit A/d Converter261................................................................................................................................................................
Overview Of The 10-bit A/d Converter262................................................................................................................................................................
Registers Of The 10-bit A/d Converter263................................................................................................................................................................
A/dc Control Register (adcth, Adctl)264................................................................................................................................................................
Software Conversion Analog Input Select Register266................................................................................................................................................................
A/d Conversion Result Register (channels 0 To 9)267................................................................................................................................................................
A/d Converter Test Register268................................................................................................................................................................
Operation Of The 10-bit A/d Converter269................................................................................................................................................................
Chapter 13 U-timer271................................................................................................................................................................
Overview272................................................................................................................................................................
U-timer Registers273................................................................................................................................................................
U-timer Operation276................................................................................................................................................................
Chapter 14 Uart277................................................................................................................................................................
Overview Of The Uart278................................................................................................................................................................
Uart Registers280................................................................................................................................................................
Serial Mode Register (smr)281................................................................................................................................................................
Serial Control Register (scr)283................................................................................................................................................................
Serial Input Data Register (sidr)/serial Output Data Register (sodr)286................................................................................................................................................................
Serial Status Register (ssr)287................................................................................................................................................................
Uart Operation291................................................................................................................................................................
Asynchronous (start-stop Synchronization) Mode293................................................................................................................................................................
Clock Synchronous Mode294................................................................................................................................................................
Occurrence Of Interrupts And Timing For Setting Flags296................................................................................................................................................................
Example Of Using The Uart299................................................................................................................................................................
Example Of Setting U-timer Baud Rates And Reload Values301................................................................................................................................................................
Chapter 15 I 2 C Interface309................................................................................................................................................................
Bus Status Register (ibsr)311................................................................................................................................................................
Bus Control Register (ibcr)314................................................................................................................................................................
Clock Control Register (iccr)320................................................................................................................................................................
Bit Slave Address Register (itba)322................................................................................................................................................................
Bit Slave Address Mask Register (itmk)323................................................................................................................................................................
Bit Slave Address Register (isba)325................................................................................................................................................................
Bit Slave Address Mask Register (ismk)326................................................................................................................................................................
Data Register (idar)327................................................................................................................................................................
Clock Disable Register (idbl)328................................................................................................................................................................
Operation Flowcharts337................................................................................................................................................................
Chapter 16 Dma Controller (dmac)341................................................................................................................................................................
Overview Of The Dma Controller (dmac)342................................................................................................................................................................
Dma Controller (dmac) Registers344................................................................................................................................................................
Control/status Registers A (dmaca0 To Dmaca4)346................................................................................................................................................................
Control/status Registers B (dmacb0 To Dmacb4)351................................................................................................................................................................
All-channel Control Register (dmacr)360................................................................................................................................................................
Other Functions362................................................................................................................................................................
Dma Controller Operation363................................................................................................................................................................
Setting A Transfer Request366................................................................................................................................................................
Transfer Sequence368................................................................................................................................................................
General Aspects Of Dma Transfer373................................................................................................................................................................
Addressing Mode375................................................................................................................................................................
Data Types376................................................................................................................................................................
Transfer Count Control377................................................................................................................................................................
Cpu Control378................................................................................................................................................................
Hold Arbitration379................................................................................................................................................................
Operation From Starting To End/stopping380................................................................................................................................................................
Dmac Interrupt Control384................................................................................................................................................................
Channel Selection And Control385................................................................................................................................................................
Supplement On External Pin And Internal Operation Timing387................................................................................................................................................................
Data Bus395................................................................................................................................................................
Chapter 17 Usb Function399................................................................................................................................................................
Overview Of The Usb Function400................................................................................................................................................................
Usb Interface Registers403................................................................................................................................................................
Data Transmission Registers (for End Points)406................................................................................................................................................................
Status Registers409................................................................................................................................................................
Control Registers416................................................................................................................................................................
Operation Of The Usb Function431................................................................................................................................................................
Flow Of Data Transfer432................................................................................................................................................................
Cpu Access Operation438................................................................................................................................................................
Interrupt Sources445................................................................................................................................................................
Setting Of End Point Buffer446................................................................................................................................................................
Examples Of Software Control448................................................................................................................................................................
Supplementary Notes On The Usb Function457................................................................................................................................................................
Double Buffer458................................................................................................................................................................
Controlling The D+ Terminating Resistor On The Board463................................................................................................................................................................
Automatic Response Of Macro Program To Usb Standard Request Commands464................................................................................................................................................................
Usb Function Macro Program Operation In The Default Status466................................................................................................................................................................
Usb Clock Control In The Suspended Status467................................................................................................................................................................
Detection Of Usb Connector Connection And Disconnection468................................................................................................................................................................
Accuracy Of Uclk48469................................................................................................................................................................
Setting Of Transfer Enable Bit (bfok) During Control Transfer470................................................................................................................................................................
Precautions For Control Transfer471................................................................................................................................................................
Macro Program Status After Usb Bus Reset473................................................................................................................................................................
Chapter 18 Osdc475................................................................................................................................................................
On-screen Display Controller (osdc)476................................................................................................................................................................
Display Functions480................................................................................................................................................................
Screen Configuration481................................................................................................................................................................
Screen Display Modes484................................................................................................................................................................
Screen Output Control486................................................................................................................................................................
Screen Display Position Control487................................................................................................................................................................
Font Memory Configuration497................................................................................................................................................................
Display Memory (vram) Configuration498................................................................................................................................................................
Writing To Display Memory (vram)499................................................................................................................................................................
Palette Configuration502................................................................................................................................................................
Character Display503................................................................................................................................................................
Character Background Display537................................................................................................................................................................
Line Background Display546................................................................................................................................................................
Screen Background Display555................................................................................................................................................................
Sprite Character Display560................................................................................................................................................................
Control Functions564................................................................................................................................................................
Dot Clock Control565................................................................................................................................................................
Sync Signal Input570................................................................................................................................................................
Display Signal Output578................................................................................................................................................................
Display Period Control581................................................................................................................................................................
Synchronization Control583................................................................................................................................................................
Interrupt Control586................................................................................................................................................................
Osdc Operation Control589................................................................................................................................................................
Display Control Commands591................................................................................................................................................................
List Of Display Control Commands592................................................................................................................................................................
Vram Write Address Set (command 0)594................................................................................................................................................................
Character Data Set (commands 1 And 2)595................................................................................................................................................................
Line Control Data Set (commands 3 And 4)597................................................................................................................................................................
Screen Output Control (commands 5-00 And 5-1)599................................................................................................................................................................
Display Position Control (commands 5-2 And 5-3)601................................................................................................................................................................
Character Vertical Size Control (command 6-0)602................................................................................................................................................................
Shaded Background Frame Color Control (command 6-1)603................................................................................................................................................................
Transparent/translucent Color Control (command 6-2)604................................................................................................................................................................
Graphic Color Control (command 6-3)605................................................................................................................................................................
Screen Background Character Control (commands 7-1 And 7-3)607................................................................................................................................................................
Sprite Character Control (commands 8-1, 8-2, 9-0 And 9-1)609................................................................................................................................................................
Synchronization Control (command 11-0)612................................................................................................................................................................
I/o Pin Control (commands 13-0 And 13-1)613................................................................................................................................................................
Display Period Control (commands 14-0 To 14-3)615................................................................................................................................................................
Interrupt Control (command 15-0)618................................................................................................................................................................
Palette Control (commands 16-0 To 16-15)619................................................................................................................................................................
Osdc Operation Control (commands 17-0 And 17-1)621................................................................................................................................................................
Plla Clock Control (commands 18-0 To 18-3)623................................................................................................................................................................
Pllb Clock Control (commands 18-4 To 18-7)625................................................................................................................................................................
Pllc Clock Control (commands 18-8 To 18-11)627................................................................................................................................................................
Clock Selection Control (commands 18-12 To 18-13)629................................................................................................................................................................
Display Control Command (cc)631................................................................................................................................................................
Cc Screen And Display Control Command List632................................................................................................................................................................
Vram Write Address Setting (command 0)633................................................................................................................................................................
Character Data Setting (command 1, Command 2)634................................................................................................................................................................
Line Control Data Setting (command 3, Command 4)636................................................................................................................................................................
Display Output Control (command 5-00, Command 5-1)638................................................................................................................................................................
Display Position Control (command 5-2, Command 5-3)640................................................................................................................................................................
Transparent Color Control (command 6-2)642................................................................................................................................................................
Display Period Control (command 14-0, 14-1, 14-2, 14-3)643................................................................................................................................................................
Palette Control (command 16-0 To Command 16-15)646................................................................................................................................................................
Font Ram Interface647................................................................................................................................................................
Chapter 19 Flash Memory651................................................................................................................................................................
Outline Of Flash Memory652................................................................................................................................................................
Flash Memory Registers659................................................................................................................................................................
Flash Control/status Register (flcr)660................................................................................................................................................................
Flash Memory Wait Register (flwc)662................................................................................................................................................................
Flash Memory Access Modes664................................................................................................................................................................
Automatic Algorithm Of Flash Memory666................................................................................................................................................................
Execution Status Of The Automatic Algorithm670................................................................................................................................................................
Writing To And Erasing From Flash Memory675................................................................................................................................................................
Read/reset Status676................................................................................................................................................................
Data Writing677................................................................................................................................................................
Data Erasure (chip Erasure)679................................................................................................................................................................
Data Erasure (sector Erasure)680................................................................................................................................................................
Temporary Sector Erase Stop682................................................................................................................................................................
Sector Erase Restart683................................................................................................................................................................
Chapter 20 Serial Programming Connection685................................................................................................................................................................
Serial Programming Connection686................................................................................................................................................................
Appendix691................................................................................................................................................................
Appendix A I/o Map692................................................................................................................................................................
Appendix B Interrupt Vector707................................................................................................................................................................
Appendix C Dot Clock Generation Pll710................................................................................................................................................................
Appendix D Usb Clock712................................................................................................................................................................
Appendix E Macro Reset713................................................................................................................................................................
Appendix F Usb Low-power Consumption Mode714................................................................................................................................................................
Appendix G External Bus Interface Setting715................................................................................................................................................................
Appendix H Pin State List717................................................................................................................................................................
Appendix I Instruction Lists721................................................................................................................................................................
I.1 How To Read The Instruction Lists722................................................................................................................................................................
I.2 Fr Family Instruction Lists726................................................................................................................................................................
Index743................................................................................................................................................................

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