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CHAPTER 3 CPU AND CONTROL UNITS
3.11.1
PLL Controls
The operation (oscillation) enable and disable and multiply-by-rate setting can be
independently controlled for each of the PLL oscillator circuits provided for each of
main source clock and subclock. Each control is set in the clock source control register
(CLKR).
This section describes each control.
■ PLL Operation Enable
To enable or disable the main PLL oscillator circuit operation, set bit10 (PLL1EN bit) of the clock
source control register (CLKR).
To enable or disable the subclock oscillator circuit operation, set bit11 (PLL2EN bit) of the clock
source control register (CLKR).
After a setting initialization reset (INIT), bits PLL1EN and PLL2EN are initialized to 0, causing the
PLL oscillator circuit operation to stop. While it is stopped, PLL output cannot be selected as the
source clock.
When the program operation starts, set the multiply-by rate of the PLL to be used as the clock
source, enable it, and switch the source clock after the PLL lock wait time elapses. For the PLL
lock wait time, use of a time base timer interrupt is recommended.
While PLL output is selected as the source clock, the PLL cannot be stopped (writing to the
register is disabled). To stop a PLL upon transition to stop mode, reselect as the source clock the
main clock divided by two before stopping the PLL.
If bit0 (OSCD1 bit) or bit1 (OSCD2 bit) of the standby control register (STCR) is set to stop
oscillation in stop mode, the corresponding PLL automatically stops when the device enters stop
mode. As a result, you do not need to set operation stop. When the device returns from stop
mode later, the PLL automatically restarts the oscillation operation. If oscillation is not set to stop
in stop mode, the PLL does not automatically stop. In this case, set operation stop before
transition to stop mode as required.
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