Fujitsu MB91319 Series Hardware Manual page 237

■ Hold Request Cancellation Request Sequence
RUN
CPU
Bus access request
DHREQ
DHACK
IRQ
LEVEL
MHALTI
If an interrupt request occurs, the interrupt level changes. If the interrupt level is higher than the
level defined in the HRCL register, MHALT1 becomes active for DMA. This causes DMA to
cancel an access request and the CPU to return from the hold state to perform the interrupt
processing.
Figure 9.4-3 shows an example of the timing chart for multiple interrupts.
Figure 9.4-3 Example of Interrupt Level HRCL < ICR (Interrupt I) < ICR (Interrupt II)
RUN
CPU
Bus access request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
❍ Example of Interrupt Routine
(1), (3) Interrupt source clear
to
(2), (4) RETI
In the above example, while Interrupt Routine I is being executed, an interrupt with a higher
priority occurs. While the interrupt with a higher level than the level in the HRCL register remains,
DHREQ is low.
Note:
Be especially careful about the relationship between interrupt levels defined in the HRCL register
and ICR.
Figure 9.4-2 Interrupt Level HRCL < ICR (LEVEL)
Bus hold Interrupt processing
(1)
Bus hold Interrupt I
CHAPTER 9 INTERRUPT CONTROLLER
(2)
Interrupt Interrupt
processing II processing I
(3) (4) (1)
Bus hold
(DMA transfer)
Example of
interrupt routine
(1) Interrupt
source clear
|
(2) RETI
Bus hold
(DMA transfer)
(2)
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